Proposed Project Work

A Parallelized Distance Transformation

Architecture for FPGAs
Abstract:
FPGA based distance transform implementation
is proposed to be used in object recognition and
shape matching systems. The proposed method
is designed to meet high performance, low
power and low area requirements. The Xilinx
Spartan-6 FPGA is preferred
for the implementation
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PROJECT FLOW

MODULES OF
ARCHITECTURE
Camera and DDR2 Control
Preprocessing
Object detection and Distance Transform
DVI driver module

CAMERA and DDR2

CONTROL
CAMERA CONTROL
Configures MT9D112 which is a CMOS image sensor
with an integrated advanced camera system and
provides a simple interface for reading the video
data
FRAME BUFFER CONTROL
Frame buffer controller operates as an interface for
accessing a DDR2 external memory. It organizes
read and write memory addressing.
Video frames are captured from MT9D112 camera
using the camera controller and buffered in DDR2
memory using frame buffer controller
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PREPROCESSING
Convert image provided by camera controller

into gray
Additionally, noise filtering is applied to gray
scale images for the accuracy of the
subsequent stages.

OBJECT DETECTION
Background subtraction method is used for

moving object detection

Background subtraction technique builds a
representation of the scene and then finds
deviations from the model for each incoming
frame
Background scene is built through averaging
of several successive frames to handle time
varying background scenes. This task is called
background training.
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OBJECT DETECTION
Background training step takes a single frame

and this frame is stored in external DDR2 RAM

as a reference frame. Once the background
model is obtained, classification of each pixel
in the current frame is performed.
The absolute difference between the current
frame
and the background model is used to specify
objects
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MORPHOLOGICAL
CLEANING
It is performed to eliminate noise from the
output binary images of detection algorithm.

MORPHOLOGICAL
CLEANING
The pipelined array architecture consumes only
LUT resources of the FPGA
This three stage array architecture allows us to
access all relevant pixels in parallel during
morphological cleaning process.
Demultiplexer selects the proper array for the
incoming new pixel.
All the pixels in binary image are written to the
relevant array in order. If eight neighbors of the
relevant pixel are written to the array architecture,
morphological operation is done for that pixel.
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DVI DRIVER
DVI driver module sends distance transform

output of images to HDMI port.

Video timing controller
It generates the proper synchronization
signals according to the selected DVI
resolution
DVI transmitter
It takes video data with proper sync signals
and transmits them through a DVI/HDMI port
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DISTANCE TRANSFORM
The city block distance transform is applied

by3x3 neighborhood mask (a = 1) where the

corner elements of the mask are ignored (b =
0).
The image is translated by propagating local
distances first in backward direction and then
in forward direction using backward and
forward masks.

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DISTANCE TRANSFORM
Infinite value is assigned to all foreground pixels

at initial state and then backward and forward

masks are propagated on the whole image.
In backward propagation, the input pixel is
compared with its upper and left neighbors. The
pixels backward distance value equals to one
plus the minimum distance value of its backward
neighbors.
Like wise, in forward propagation the input pixel
is compared with its lower and right neighbors.
The pixels forward distance value equals to one
plus the minimum distance value of its forward
neighbors.
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CIRCUIT IMPLEMENTATION OF FORWARD

AND BACKWARD PROPAGATION
Shift Register Array(SRA) is used to store

updated distance transform values. The size

of the SRA is WX9 bits where W is the width of
the input image.

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PROCESS STEPS OF
STANDARD
DT of the sequential
In standard methodology
type distance transform, forward propagation
CALCULATIONS
step waits for all pixels to complete the
backward propagation step.
The backward propagation outputs are written
to an internal block RAM and then forward
mask is propagated on it. The distance
transform calculation takes WXHX2 clock
cycles for a single frame with this standard
type, where W and H are the width and height
of the image respectively
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PROCESS STEPS OF
PARALLELISED
DT
Instead of waiting for all pixels to complete
CALCULATIONS
backward propagation step, predetermined
number of pixels are waited to finish the
backward propagation and these pixels are
considered to be a new sub-frame for the
forward propagation step.

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PARALLELISED DISTANCE
The system waits for all sub-frames of a single
TRANSFORM

frame to complete the forward propagation step.

Then the process cycle restarts for the next frame
while the combiner step joins all the sub-frames.
The combiner step, as the final step, calculates the
final distance transform output for each sub-frame
using
Pixel value = min{border value +distance from the
border pixel value}.
The distance transform values are compared with
the border values of the other sub-frames by adding
the distance from the borders. If the value is higher
than the one of the cumulative values, it is updated.
This step is done for all sub-frames sequentially
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PARALLELISED DISTANCE
TRANSFORM
The backward propagation outputs are written
to the relevant block RAM via Demultiplexer.
When backward propagation is finished for a
sub-frame, the forward propagation is started
for the relevant sub-frame. Simultaneously,
the backward propagation continues for the
new incoming pixels.
The input frame is divided into four subframes for our system. The number of subframes can be increased under the
consideration of block RAM utilization.
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PARALLELISED DISTANCE
TRANSFORM

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PARALLELISED DISTANCE
TRANSFORM
With this technique, the distance transform

process takes W x H x(n + 1)=n clock cycles,

where n is the number of sub-frames. With n
= 1, the time consumption of the novel
methodology equals to the time consumption
of the standard approach. As n increases, the
timing advantage of the new methodology
increases.

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CONSIDERATIONS ON
PAPER
Resolution of the video frames is 320 X 480.
The input frame is divided into four sub-

frames.
Implemented on Digilent Atlys board with
Spartan-6 FPGA
The whole system is operated at 98 MHz clock
frequency

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References
A parallelized distance transformation architecture

for FPGAs
Atay, M. ; Inf. & Inf. Security, Res. Center (BILGEM), Kocaeli,
Turkey ; Yalcin, M.E.
Published in:
Circuit Theory and Design (ECCTD), 2013 European Conferenc
e on
Sept. 2013