1

Features
It is a 16-bit p.
8086 has a 20 bit address bus can access up
to 220 memory locations (1 MB).
It has multiplexed address and data bus
AD0- AD15 and A16 A19.
It requires +5V power supply.
A 40 pin dual in line package.

 8086 is designed to operate in two modes,

Minimum and Maximum.
It can prefetches up to 6 instruction bytes
from memory and queues them in order to
speed up instruction execution.
Address ranges from 00000H to FFFFFH
Memory is byte addressable - Every byte has a
separate address.

Intel 8086 Internal Architecture

Internal architecture of 8086

8086 has two blocks BIU and EU.
The BIU handles all transactions of data and
addresses on the buses for EU.
The BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and calculating the
addresses of the memory operands. The
instruction bytes are transferred to the
instruction queue.
EU executes instructions from the instruction
system byte queue.
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 Both units operate asynchronously to

give the 8086 an overlapping instruction
fetch and execution mechanism which is
called as Pipelining. This results in
efficient use of the system bus and
system performance.
BIU contains Instruction queue, Segment
registers, Instruction pointer, Address
adder.
EU contains Control circuitry, Instruction
decoder, ALU, Pointer and Index register,
Flag register.
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BUS INTERFACE UNIT (BIU)

Contains
6-byte Instruction Queue (Q)
The Segment Registers (CS, DS, ES, SS).
The Instruction Pointer (IP).
The Address Summing block ()

THE QUEUE (Q)

The BIU uses a mechanism known as an
instruction stream queue to implement a pipeline
architecture.
This queue permits pre-fetch of up to 6 bytes of
instruction code. Whenever the queue of the BIU is
not full, it has room for at least two more bytes and
at the same time the EU is not requesting it to read
or write operands from memory, the BIU is free to
look ahead in the program by pre-fetching the next
sequential instruction.
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 These pre-fetching instructions are held in its FIFO

queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue,
it automatically shifts up through the FIFO to the
empty location nearest the output.
The EU accesses the queue from the output
end. It reads one instruction byte after the other
from the output of the queue.
The intervals of no bus activity, which may occur
between bus cycles are known as Idle state.
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The Queue Operation

From
memory

(Decode also decides the no. of

data bytes for the instructions)

Execute it with data bytes

decoded by the decoder
yes

Data

Update Take 2nd byte from Q as

queue opcode, decode 2nd byte
opcode

Opcode
Opcode queue

Opcode 2nd byte

Is it
Single
byte?

No
Take 2nd byte from Q as
opcode, decode 2nd byte
opcode
Execute it with data bytes
decoded by the decoder

Repeat the same procedure

for successive contents of Q

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Instruction Queue
8086 employs overlapped processing
When EU is busy decoding or executing current
instruction, the system bus of 8086 may not be in
use.
At that time, BIU can use buses to fetch up to six
instruction bytes of the instructions next in program
BIU stores these pre-fetched bytes in a FIFO register
called Instruction Queue
When EU is ready for its next instruction, it simply
reads the instruction from the queue in BIU
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Instruction Pipeline
EU of 8086 does not have to wait for
BIU to fetch next instruction byte
from memory
The presence of a queue in 8086
speeds up the processing
Fetching the next instruction while
the current instruction executes is
called Instruction look ahead
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Segmented Memory
The memory in an 8086/88
based system is organized as
segmented memory.

Physical Memory
00000

Code segment (64KB)

The CPU 8086 is able to

address 1Mbyte of memory.

1 MB

Data segment (64KB)

Extra segment (64KB)

The Complete physically

available memory may be
divided into a number of logical
segments.

Stack segment (64KB)

FFFFF
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 The size of each segment is 64 KB

A segment is an area that begins at any location which is
divisible by 16.
A segment may be located any where in the memory
Each of these segments can be used for a specific
function.
Code segment is used for storing the instructions.
The stack segment is used as a stack and it is used to store the
return addresses.
The data and extra segments are used for storing data byte.

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 The 4 segments are Code, Data, Extra and Stack segments.

A Segment is a 64kbyte block of memory.
The 16 bit contents of the segment registers in the BIU
actually point to the starting location of a particular segment.
Segments may be overlapped or non-overlapped

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Segment registers
In 8086/88 the processors have 4 segments
registers
Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
All are 16 bit registers.
Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.
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17

Instruction pointer & summing block

The instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
The IP always references the Code segment register
(CS).
The value contained in the instruction pointer is called
as an offset because this value must be added to the
base address of the code segment, which is available in
the CS register to find the 20-bit physical address.
The value of the instruction pointer is incremented after
executing every instruction.
To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing
block) to the address contained in the CS , which has
been shifted four bits to the left.
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19

 The following examples shows the CS:IP scheme of

address formation:
CS

34BA

IP

8AB4

Code segment
34BA0

Inserting a hexadecimal 0H (0000B)

8AB4 (offset)

with the CSR or shifting the CSR

four binary digits left

3D645

34BA0(CS)+
8AB4( I P)
3 D 6 5 4 (next address)

44B9F
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 Example For Address Calculation (segment: offset)

If the data segment starts at location 1000h and a data
reference contains the address 29h where is the actual
data?
Offset
Segment Address

Required Address

0000 0000 0010 1001

0001 0000 0000 0000

0001

0000

0000 0000 0010 1001

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EXECUTION UNIT
Decodes instructions fetched by the BIU
Generate control signals,
Executes instructions.
The main parts are:
Control Circuitry
Instruction decoder
ALU
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EXECUTION UNIT General Purpose Registers

16 bits

AX
BX
CX
DX

8 bits

8 bits

AH

AL

BH

BL

Base

CH

CL

Count

DH

DL
SP

Pointer

BP
SI

Index

DI

Accumulator

Data
Stack Pointer
Base Pointer
Source Index
Destination Index
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EXECUTION UNIT General Purpose Registers

Register

Purpose

AX

Word multiply, word divide, word I /O

AL

Byte multiply, byte divide, byte I/O, decimal

arithmetic

AH

Byte multiply, byte divide

BX

Store address information

CX

String operation, loops

CL

Variable shift and rotate

DX

Word multiply, word divide, indirect I/O

(Used to hold I/O address during I/O instructions. If the result is more than
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16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register)

Pointer And Index Registers

used to keep offset addresses.
Used in various forms of memory addressing.
In the case of SP and BP the default reference to form a physical
address is the Stack Segment (SS-will be discussed under the
BIU)
The index registers (SI & DI) and the BX generally default to the
Data segment register (DS).
SP: Stack pointer
Used with SS to access the stack segment
BP: Base Pointer
Primarily used to access data on the stack
Can be used to access data in other segments
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 SI: Source Index register

is required for some string operations
When string operations are performed, the SI register points
to memory locations in the data segment which is addressed
by the DS register. Thus, SI is associated with
the DS in
string operations.
DI: Destination Index register
is also required for some string operations.
When string operations are performed, the DI register points
to memory locations in the data segment which is addressed
by the ES register. Thus, DI is associated with
the ES in
string operations.

The SI and the DI registers may also be used to access data

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stored in arrays

EXECUTION UNIT Flag Register

A flag is a flip flop which indicates some conditions produced by
the execution of an instruction or controls certain operations of
the EU .
In 8086 The EU contains
a 16 bit flag register
9 of the 16 are active flags and remaining 7 are undefined.
6 flags indicates some conditions- status flags
3 flags control Flags
U

Over flow

O
F

Direction

U - Unused

D
F

IF

TF SF ZF U

Interrupt Trap

Sign

A
F

PF U

Auxiliary
Zero

Parity

CF
Carry

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EXECUTION UNIT Flag Register

Flag

Purpose

Carry (CF)

Holds the carry after addition or the borrow after subtraction.

Also indicates some error conditions, as dictated by some
programs and procedures .

Parity (PF)

PF=0;odd parity, PF=1;even parity.

Auxiliary (AF) Holds the carry (half carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF)

Shows the result of the arithmetic or logic operation.

Z=1; result is zero. Z=0; The result is 0

Sign (SF)

Holds the sign of the result after an arithmetic/logic

instruction
execution. S=1; negative, S=0

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Flag

Purpose

Trap (TF)

A control flag.
Enables the trapping through an on-chip debugging
feature.

Interrupt (IF)

A control flag.
Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.

Direction (DF)

A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.

Overflow (OF)

Overflow occurs when signed numbers are added or

subtracted. An overflow indicates the result has exceeded
the capacity of the Machine
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Execution unit Flag Register

Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed

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Min/Max Pin-out Modes

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Logical Signals

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8088 Details

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Min/Max Modes
Minimum and Maximum Modes
The minimum mode is selected by applying
logic 1 to the MN / MX# input pin. This is a
single microprocessor configuration.

The maximum mode is selected by

applying logic 0 to the MN / MX# input pin.
This is a multi micro processors
configuration.

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Signal Description-1

35

Signal Description-2

36

Signal Description
Max Mode

37

Memory Organization

38

Reserved Memory
Locations

39

Min Mode Logical

Pin out

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Min Mode
Interface-1
When the Minimum mode operation is
selected, the 8086 provides all control
signals needed to implement the memory
and I/O interface
The minimum mode signal can be divided
into the following basic groups:
address/data bus, status, control, interrupt
and DMA.
Address/Data Bus : these lines serve
two functions. As an address bus is 20
bits long and consists of signal lines A0
through A19. A19 represents the MSB and
A0 LSB. A 20bit address gives the 8086 a
1Mbyte memory address space.
Independent I/O address space which 64K
bytes in length
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Min Mode
Interface-2
The 16 data bus lines D0 through D15
are actually multiplexed with address
lines A0 through A15 respectively. The
bus works as an address bus during
first machine cycle and as a data bus
during next machine cycles. D15 is
the MSB and D0 LSB
When acting as a data bus, they carry
read/write data for memory,
input/output data for I/O devices, and
interrupt type codes from an interrupt
controller
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Min Mode
Interface-3
Status signal : The four most significant
address lines A19 through A16 are also
multiplexed but in this case with status
signals S6 through S3. These status bits are
output on the bus at the same time that data
are transferred over the other bus lines.
Bit S4 and S3 together form a 2 bit binary
code that identifies which of the 8086
internal segment registers are used to
generate the physical address output on the
address bus during the current bus cycle
Code S4,S3 = 00 identifies a register known
as extra segment register as the source of
the segment address

43

Min Mode
Interface-4

44

Min Mode
Interface-5
Status line S5 reflects the status of another
internal characteristic of the 8086. It is the
logic level of the internal enable flag. The
last status bit S6 is always at the logic 0 level
Control Signals : The control signals are
provided to support the 8086 memory & I/O
interfaces. They control functions such as
when the bus is to carry a valid address, in
which direction data are to be transferred
over the bus, when valid write data are on
the bus and when to put read data on the
system bus

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Min Mode
Interface-6
ALE is a pulse to logic 1 that signals
external circuitry when a valid address
word is on the bus. This address must be
latched in external circuitry on the 1-to-0
edge of the pulse at ALE.
Another control signal that is produced
during the bus cycle is BHE bank high
enable. Logic 0 on this used as a memory
enable signal for the most significant byte
half of the data bus D8 through D1. These
line also serves a second function, which
is as the S7 status line
Using the M/IO and DT/R lines, the 8086
signals which type of bus cycle is in
progress and in which direction data are
to be transferred over the bus.
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Min Mode
Interface-7
The logic level of M/IO tells external circuitry
whether a memory or I/O transfer is taking
place over the bus. Logic 1 at this output
signals a memory operation and logic 0 an I/O
operation.
The direction of data transfer over the bus is
signalled by the logic level output at DT/R.
When this line is logic 1 during the data
transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either
written into
memory or output to an I/O device
On the other hand, logic 0 at DT/R signals that
the bus is in the receive mode. This
corresponds to reading data from memory or
input of data from an input port
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Min Mode
Interface-8
The signal read RD and write WR indicates
that a read bus cycle or a write bus cycle is
in progress. The 8086 switches WR to logic
0 to signal external device that valid write
or output data are on the bus
On the other hand, RD indicates that the
8086 is performing a read of data of the
bus. During read operations, one other
control signal is also supplied. This is DEN
( data enable) and it signals external
devices when they should put data on the
bus
There is one other control signal that is
involved with the memory and I/O
interface. This is the READY signal
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Min Mode
Interface-9
READY signal is used to insert wait states
into the bus cycle such that it is extended
by a number of clock periods. This signal
is provided by an external clock
generator device and can be supplied by
the memory or I/O subsystem to signal
the 8086 when they are ready to permit
the data transfer to be completed.
Interrupt signals : The key interrupt
interface signals are interrupt request
(INTR) and interrupt acknowledge( INTA)
INTR is an input to the 8086 that can be
used by an external device to signal that
it need to be serviced
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Min Mode
Interface-10
Logic 1 at INTR represents an active
interrupt request. When an interrupt
request has been recognized by the 8086,
it indicates this fact to external circuit with
pulse to logic 0 at the INTA output
The TEST input is also related to the
external interrupt interface. Execution of a
WAIT instruction causes the 8086 to check
the logic level at the TEST input
If the logic 1 is found, the MPU suspends
operation and goes into the idle state. The
8086 no longer executes instructions,
instead it repeatedly checks the logic level
of the TEST input waiting for its transition
back to logic 0
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Min Mode
Interface-11
As TEST switches to 0, execution resume
with the next instruction in the program.
This feature can be used to synchronize the
operation of the 8086 to an event in
external hardware.
There are two more inputs in the interrupt
interface: the non-maskable interrupt NMI
and the reset interrupt RESET
On the 0-to-1 transition of NMI control is
passed to a non-maskable interrupt service
routine. The RESET input is used to provide
a hardware reset for the 8086. Switching
RESET to logic 0 initializes the internal
register of the 8086 and initiates a reset
service routine
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Min Mode
Interface-12
DMA Interface signals :The direct memory
access DMA interface of the 8086 minimum
mode consist of the HOLD and HLDA signals
When an external device wants to take
control of the system bus, it signals to the
8086 by switching HOLD to the logic 1 level.
At the completion of the current bus cycle,
the 8086 enters the hold state. In the hold
state, signal lines AD0 through AD15, A16/S3
through A19/S6, BHE, M/IO, DT/R, RD, WR,
DEN and INTR are all in the high Z state. The
8086 signals external device that it is in this
state by switching its HLDA output to logic 1
level
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Max Mode
Block Diagram

53

Max Mode
Interface-1
When the 8086 is set for the maximummode configuration, it provides signals for
implementing a multiprocessor /
coprocessor system environment
By multiprocessor environment we mean
that one microprocessor exists in the
system and that each processor is
executing its own program
Usually in this type of system
environment, there are some system
resources that are common to all
processors
They are called as global resources. There
are also other resources that are assigned
to specific processors. These are known as
local or private resources
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Max Mode
Interface-2
In multiple processor situation a
second processor is in the system.
Both processors do not access the
bus at the same time
One passes the control of the system
bus to the other and then may
suspend its operation
In the maximum-mode 8086 system,
facilities are provided for
implementing allocation of global
resources and passing bus control to
other microprocessor or coprocessor.
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Max Configuration
Using 8288 Bus Controller

56

8288 Pin out

57

Max Mode
Interface-3

58

Max Mode
Interface-4
The 8288 produces one or two of these eight
command signals for each bus cycles. For
instance, when the 8086 outputs the code
S2S1S0 equals 001, it indicates that an I/O
read cycle is to be performed
If the code 111 is output by the 8086, it is
signalling that no bus activity is to take place
The control outputs produced by the 8288
are DEN, DT/R and ALE. These 3 signals
provide the same functions as those
described for the minimum system mode.
This set of bus commands and control signals
is compatible with the Multibus (an industry
standard) for interfacing microprocessor
systems.
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Max Mode
Interface-5
8289 Bus Arbiter Bus Arbitration and
Lock Signals : This device permits processors
to reside on the system bus. It does this by
implementing the Multibus arbitration
protocol in an 8086-based system
Addition of the 8288 bus controller and 8289
bus arbiter frees a number of the 8086 pins
for use to produce control signals that are
needed to support multiple processors
Bus priority lock ( LOCK) is one of these
signals. It is input to the bus arbiter together
with status signals S0 through S2.

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8289 Pin Out

61

Max Mode
Interface-6
The output of 8289 are bus arbitration
signals: bus busy (BUSY), common bus
request (CBRQ), bus priority out (BPRO),
bus priority in (BPRN), bus request
(BREQ) and bus clock (BCLK).
They correspond to the bus exchange
signals of the Multibus and are used to
lock other processor off the system bus
during the execution of an instruction by
the 8086
In this way the processor can be assured
of uninterrupted access to common
system resources such as global
memory.
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Max Mode
Interface-7
Queue Status Signals : Two new signals
that are produced by the 8086 in the
maximum-mode system are queue status
outputs QS0 and QS1. Together they form
a 2-bit queue status code, QS1QS0
Following table shows the four different
queue status

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Max Mode
Interface-8
Local Bus Control Signal Request /
Grant Signals: In a maximum mode
configuration, the minimum mode HOLD,
HLDA interface is also changed. These
two are replaced by request/grant lines
RQ/ GT0 and RQ/ GT1, respectively. They
provide a prioritized bus access
mechanism for accessing the local bus.
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Instruction Set

65

Instruction Format

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Addressing Modes
Addressing mode indicates a way of
locating data or operands
Depending upon the data types used in
the instruction and the memory
addressing modes, any instruction may
belong to one or more addressing
modes, or some instruction may not
belong to any of the addressing modes
Addressing modes describe the types of
operands and the way they are accessed
for executing an instruction. Instructions
may be categorized as
Sequential control flow instructions and
Control transfer instructions
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Instruction Type Modes

Sequential control flow instructions are
the instructions, which after execution,
transfer control to the next instruction
appearing immediately after it (in
sequence) in the program
For example, the arithmetic, logical, data
transfer and processor control instructions
are sequential control flow instructions

The control transfer instructions, on the

other hand, transfer control to some
predefined address somehow specified in
the instruction after their execution. For
example, INT, CALL, RET and JUMP
instructions fall under this category
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