PROJECT TITLE

Physical implementation challenges, Timing and power optimization

of high frequency functional blocks in deep-submicron technology

Rama Krishna P.
CGB0911012, FT-2011
M. Sc. [Engg.] in VLSI System Design

M. S. Ramaiah School of Advanced Studies

AIM

To implement and optimize the Timing and power in high frequency

Latch based design in deep sub micron technology with effective
methods in the Physical synthesis of the design

M. S. Ramaiah School of Advanced Studies

INTRODUCTION

CMOS technology scaling has over the past brought gains in cost, complexity, speed and power.
However, with the event of nanoscale dimensions, new phenomena appear and cause many
substantial problems.
In digital field, other trends like low power in embedded systems can amplify those effects. For
instance, decreasing the power supply voltage has a direct consequence on the sensitivity to
variability.
Among all the faults which can defect a digital chip, setup and hold time violations are the most
representative. Setup time violations induce lower performances in power, consumption or
throughput, whereas hold time violations can seriously impact production yield.

M. S. Ramaiah School of Advanced Studies

INTRODUCTION
Processor design flow is broadly divided into two parts
Front-end:

Deals with architectural design, micro-architectural details, coding in

hardware description language, validation, etc..

Back-end:

It deals with the implementation of the front-end code and convergence

Chip hierarchy in back-end for processor Design

Full chip
Unit
Cluster
Functional unit block (FUB)
Figure 1 Hierarchy levels in chip design

M. S. Ramaiah School of Advanced Studies

BACKEND RLS FLOW

The high level overview of the RLS flow steps is
given with the diagram in Figure 2.
The RLS flow is run at the fub level, and the
main inputs are the fub RTL, timing constraints and
floorplan data.

Figure 2 RLS flow steps (Branimir Malnar 2012)

M. S. Ramaiah School of Advanced Studies

LITERATURE REVIEW
Upto 20% performance boost using latches as compared to flip-flop based designs for a small area
penalty for several configurations of Xtensa embedded processor. Their approach consists of doubling
the pipeline stages, retiming the design and then replacing flip flops by latches (Charwak et al., 2009)
The timing of the logic after the latch is dependent on the timing of logic preceding the latch.
Furthermore, these dependencies can be circular. Because of this difficultly, the analysis of latch-based
timing is significantly more complicated than for register-based designs (Carl Ebeling et al., 2005)
Latch-based design has the advantage of being more tolerant to imbalances in the delays between
adjacent paths. For two adjacent paths to operate at the mean of their delays, the arrival of the clock at
a register between them must be scheduled at exactly the balancing point; the arrival of the clock at a
latch between them must only be scheduled so that the balancing point falls somewhere within the
transparent window (Aaron P. Hurst et al.)
Many researchers have conducted research in timing analysis for latch-based designs in the early 90s.
However, prior works are based on fixed-delay timing models that may no longer be effective to
represent the timing behavior of todays deep sub-micron (DSM) designs (Mango C.-T. Chao et al.)

M. S. Ramaiah School of Advanced Studies

LITERATURE REVIEW
In all of the earlier work (Sakallah et al. 1990a,b; Szymanski and Shenoy 1992; Szymanski 1992;
Lee et al. 1994), a multiphase non-overlapped clock scheme with a common clock cycle is assumed.
This cannot be applied to a general clock scheme such as clocks with different cycle times, multicycle paths and false paths. An efficient way of doing static timing analysis with known false paths
is presented in Belkhale and Suess. It can be extended to handle known paths with other constraints
such as multi-cycle paths. However, time borrowing was not addressed (Shi-zheng Eric Lin et al.)
Current non-statistical timing tools can not even account for the tolerance to timing variation that
level-sensitive clocking allows, let alone optimize the schedule appropriately in process variation.
The current results indicate some promise along both fronts, but the problem is significantly
challenging, and more is definitely to be done (Aaron P. Hurst)
One reason is that microprocessor projects take much longer compared to some other simpler chips.
For that reason, microprocessors are not adopting the newest DC (Design Compiler) and ICC
(Synopsys Compiler) versions immediately upon their release, because it takes some time to test the
existing RLS flow with the new tool versions, and to fully adopt them (Branimir Malnar 2012)

M. S. Ramaiah School of Advanced Studies

LITERATURE REVIEW
Existing dual-Vth based registers reduce the leakage current only along the feedback path to not
affect the timing constraints. This traditional approach significantly limits the amount of leakage that
can be reduced, particularly in sub 22 nm CMOS technologies. Furthermore, in conventional
approaches, the hold time of the register may be affected which may produce a timing violation
depending upon the type of timing path and register ( P.Sreenivasulu et al., 2013)
Reducing power in the clock network can impact the overall dynamic power significantly. Designers
already use a variety of techniques to reduce the clock power using smaller clock buffers, reducing
the overall wiring capacitance, employing clock gating to reduce the dynamic power, and de-cloning
to move the clock buffers at higher levels of hierarchy (P.Sreenivasulu et al., 2013)

M. S. Ramaiah School of Advanced Studies

OBJECTIVES

To carryout literature survey of different methods and flows for optimizing timing
problems in the Latch based design and different methods for reducing the power of the
high frquency Latch based designs in deep sub-micron.

To arrive at the timing and power results with effective RLS physical design flow for
Latch based design

To resolve the time scheduling problems in three cycle pipeline latch based designs with
balancing the power in the deep sub micron technology

To implement the different methods for optimizing the timing violations and slope issues
in Latch based design without effecting the logic of the design

To implement the effective methods for reducing the both leakage and dynamic power of
the latch based design

To arrive at the best methods for balancing the tradeoff between power and timing in
latch based design

M. S. Ramaiah School of Advanced Studies

METHODS and METOHDOLOGY

Literature survey will be carried out on current methods and flows for optimizing the
timing in the deep sub micron latch based designs
Literature survey will be carried out on current methods and different cells for optimizing
the power in the deep sub micron latch based designs
Based on the reviewed literature and IEEE Journals the shortcomings of the existing
methods and challenges to optimize timing, power and layout issues will be carried out
The collection of all inputs (floorplan, placement, CTS, route..etc) to the design will be
carried out and the flow setup will be carried out
The physical synthesis will be carried out from RTL to physical design with design for
manufacturability stage
The analysis of the all path which are violating timing will be carried out and the power
analysis also will be carried out
The techniques for time scheduling for the larger cell count lacth based designs will be
analyzed on all types of paths which design has three cycle pipeline model.
M. S. Ramaiah School of Advanced Studies

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METHODS and METOHDOLOGY

Some other methods for optimizing the slope, skew and other constraints will be identified

The internal max timing violations will be solved by using effective methods
The internal min timing violations will be solved by using effective methods
The external timing violations will be solved by effective methods
The power analysis will be carried out for the design based on different traces which
giving more active factor and AQM
Different techniques will be carried out for reducing the leakage power in the design
Different techniques will be carried out for reducing dynamic power in the design
After applying different power optimized techniques, timing and power tradeoff will be
analyzed
Finally from All the methods which are useful for the specific design will be carried out
without effecting the logic of the design

M. S. Ramaiah School of Advanced Studies

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RESOURCES
Software

Industrial tools

Literature

Journal and Conference Papers

Books

Websites

M. S. Ramaiah School of Advanced Studies

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PROJECT SCHEDULE

M. S. Ramaiah School of Advanced Studies

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REFERENCE
Mango C.-T. Chao et al., (n.d.) Static Statistical Timing Analysis for Latch-based Pipeline Designs
Department of ECE, UC-Santa Barbara Intel Corporation, Austin, Texas
Aaron P. Hurst et al., (n.d.) Latch/Register Scheduling For Process Variation Dept. of Electrical
Engineering and Computer Sciences University of California, Berkeley
SHI-ZHENG ERIC LIN et al., (2002) Optimal Time Borrowing Analysis and Timing Budgeting
Optimization for Latch-Based Designs ACM Transactions on Design Automation of Electronic
Systems, Vol. 7
P.Sreenivasulu et al., (2013) Power Optimization Technique for Pulsed Latches International
Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-3, Issue-1
Vladimir Stojanovic et al., (1999) Comparative Analysis of MasterSlave Latches and Flip-Flops for
High-Performance and Low-Power Systems IEEE JOURNAL OF SOLID-STATE CIRCUITS,
VOL. 34, NO. 4
Abde Ali et al., (2009) Investigation of Latch based Design Group 15:Charwak and Abde Ali
B. Rebaud et al., (2008) Setup and Hold Timing Violations Induced by Process Variations in a Digital
Multiplier IEEE Computer Society Annual Symposium on VLSI, ISVLSI.2008.70

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REFERENCE
Branimir Malnar (2012) Synthesis Flow for Designing a High Performance Microprocessor MIPRO
2012, May 21-25,2012, Opatija, Croatia
Emre Salman et al., (2006) Pessimism Reduction In Static Timing Analysis Using Interdependent
Setup and Hold Times IEEE, Proceedings of the 7th International Symposium on Quality
Electronic Design (ISQED06)
Emre Salman et al., (2007) Exploiting SetupHold-Time Interdependence in Static Timing Analysis
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND
SYSTEMS, VOL. 26, NO. 6
Hong-Yean Hsieh et al., (2010) Integrated Parametric Timing Optimization of Digital Systems IEEE
TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND
SYSTEMS, VOL. 19, NO. 4
Michael J. Flynn et al., (1999) DEEP-SUBMICRON MICROPROCESSOR DESIGN ISSUES IEEE
MICRO 0272-1732/99
Pinaki Chakrabarti et al., (2010) Clock Tree Skew Minimization with Structured Routing IEEE, 2012
25th International Conference on VLSI Design

M. S. Ramaiah School of Advanced Studies

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Roopa Chari (n.d.) Timing and Clocking Issues [ONLINE] available from <
http://sequoia.ece.ucsb.edu/ece152B/notes/FILES/TimingNotes_2006.pdf
>
[20
MAY2013]
Ying-Yu Chen et al., (2010) Clock Tree Synthesis under Aggressive Buffer Insertion DAC10,
June, 2010, Anaheim, CA, USA.Copyright 2010 ACM 1-58113-000-0/00/0010

M. S. Ramaiah School of Advanced Studies

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BENEFITS OF THE WORK

Will it result into a publication? Yes

Will it result into a product? Yes
Will it be a solution to an existing problem of an industry? Yes
Is it pursued for academic interest? Yes

M. S. Ramaiah School of Advanced Studies

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