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Timing Analysis
Prerequisites
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Objective
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Scope
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Day 1
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Functional
Specifications
RTL
GDS-II
Timing
Specifications
Functional
Verification
GLS
LEC
STA
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Each component has its own limit which are bound by the variations in
the operating environment.
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Corner Analysis
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Design Corners
Typical Corner :
Checks for both Hold and Setup Time.
Provides an approximate estimate of the frequency that can be met
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Timing Fundamentals
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Concept of D Latch
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D Input must not change in the (shaded) window of time around the
falling edge of C.
If D changes at any time during the setup- and hold- time window, the
output of the latch is unpredictable and may become metastable.
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Metastability
Metastability is the state that exist between either valid digital logic
state.
Digital circuits have two stable states - but all have a third metastable
state halfway between 0 and 1.
When the setup and hold times of a latch/flip-flop are not met, it could
be put into the metastable state.
Noise will be amplified and push the latch/flip-flop one way or other.
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It has a setup- and hold-time window during which the D input must not
change.
This window occurs around the triggering edge of CLK.
If setup and hold times are not met, the flip-flop output goes to
metastable state.
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Timing Analysis
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An example circuit
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Break the design into Fan-in Cone for each destination flop .
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An STA tool
Takes in a circuit and its timing constraints
Computes its performance bounds
Compares them against its timing constraints
Outputs a pass or fail
[Source : http://www.tauworkshop.com/04_Slides/Tseng-False.pdf]
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Advantages:
Speed (Faster than dynamic simulation)
Capacity of handling full chip
Exhaustive Timing coverage
Vectors not required
Process variation across die can be modeled
Assertions and reports are concise and easy to interpret
Disadvantages:
Pessimistic (too conservative).
If you are doing worst case analysis then path delay considered is worst
for all the elements within the path where-as in actual scenario it might
not be so worse.
It might happen that the PVT may not correspond to the real working
environment but still we need to close timing in all corners.
Difficult to get correct timing models/parameters for Analog components to
perform STA. Not a limitation from STA tool point of view.
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Inputs
Outputs
Reports : The timing paths report which can be used for analyzing.
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Timing Analysis
Introduction
Basic
Advance
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Timing Analysis
Introduction
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Delays
Gate delay
Transistors within a gate, take a finite amount of time to switch. This
means that a change on the input of a gate takes a finite amount of time
to cause a change on the output.
Net delay
The delay between the time a signal is first applied to the net and the
time it reaches other devices connected to that net.
A
Stage Delay
A
VDD
Y
A
Gate
delay
Net delay
(Interconnect)
Y
VSS
Transistor
Representation
Gate Delay
Delay through a cell is often determined by the cells intrinsic delay, load
that it is driving, and input transition (slew)
Transition is the time it takes for the pin to change state
A
Propagation Delay (inverting)
Voltage
Vmax
Voltage
Input Signal
Vmin
Output Signal
50%
Vmax
90%
10%
Cell Delay
Slew
Time
Vmin
Input Signal
50%
Output Signal
90%
10%
Cell Delay
Slew
Time
Net Delay
A
v -> v
^ -> ^
v -> v
50%
50%
Net Delay
Net Delay
50%
50%
Timing Paths
What is timing point ?
Node at which timing data is present
What is a Timing path?
A timing path is a point-to-point path in a design which can
propagate data from from one flip-flop to another
Each path has a startpoint and an endpoint
Startpoints (Input ports, Clock pins of flip-flops)
Endpoints ( Output ports, Data input pins of flip-flops)
Timing Point
INPUT
CLOCK
07/25/15 - page 32
D
Q
FF1
D
Q
FF2
OUTPUT
CLK
PRE
D
Tsu Th
Q
CLR
DATA
Valid
Setup Time: the amount of time the synchronous input (D) must be stable
before the active edge of clock
Hold Time: the amount of time the synchronous input (D) must be stable
after the active edge of clock.
Together, the setup time and hold time form a Data Required Window, the
time around a clock edge in which data must be stable.
Setup Time
Setup Margin
The data valid time available after meeting the setup requirement
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Hold Time
Hold Margin
The data valid time available after meeting the hold requirement
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Lab Session 1
For a sequential circuit, the following timing parameters are given tcomb = 1 ns, min and 8 ns, max
tffpd = 2 ns, min and 10 ns, max
tsetup = 2 ns, min & max
thold = 1 ns, min & max
Calculate Setup Margin at 25 Mhz clk frequency, Maximum frequency and
the hold margin?
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Day 2
07/25/15 - page 38
Timing Analysis
Basics
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07/25/15 - page 41
Comb.
Logic
PRE
Tclk1
Tdata
CLR
REG2
PRE
Q
CLR
TCO
Launch
Edge
Tclk1
REG1.CLK
Tco
REG1.Q
Data Valid
Tdata
REG2.D
Data Valid
REG1
PRE
REG2
Comb.
Logic
PRE
CLR
Q
CLR
Tclk2
Latch
Edge
CLK
REG2.CLK
[Source : Alteras Timing Analysis Introduction presentation]
07/25/15 - page 43
Tclk2
The minimum time required for the data to get latched into the destination
register
Data Required Time = Clock Arrival Time Tsu
REG1
PRE
REG2
Comb.
Logic
PRE
CLR
Q
CLR
Tclk2
Latch
Edge
CLK
Tclk2
Data must be
valid here
Tsu
REG2.CLK
REG2.D
Data Valid
The minimum time required for the data to get latched into the
destination register
Data Required Time = Clock Arrival Time + Th
REG1
PRE
REG2
Comb.
Logic
PRE
CLR
CLR
Tclk2
CLK
Data must
remain valid
to here
Tclk2
Th
REG2.CLK
REG2.D
Data Valid
Th
Latch
Edge
Setup Slack
Tdata
Comb.
Logic
PRE
Tclk1
PRE
CLR
CLK
REG1.CLK
Tclk2
Tclk1
Tco
Data Valid
Tdata
REG2.D
Data Valid
Tclk2
Tsu
Setup
Slack
Tsu
Latch
Edge
REG1.Q
REG2.CLK
Q
CLR
TCO
Launch
Edge
REG2
CALCULATION:
Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)
Required time = clock adjust + clock delay FF2 (min) - set up time FF2
Slack = Required time - Arrival time (since we want data to arrive before it is required)
clock adjust = clock period (since setup is analyzed at next edge)
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Hold Slack
Tclk1
Comb.
Logic
Tdata
REG2
PRE
CLR
Q
CLR
TCO
Tclk2
Th
Next Launch
Edge
CLK
Latch
Edge
Tclk1
REG1.CLK
REG1.Q
Tco
Data Valid
Tdata
REG2.D
Data Valid
Tclk2
REG2.CLK
Th
Hold
Slack
CALCULATION:
Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)
Required time = clock adjust + clock delay FF2 (max) + hold time FF2
Slack = Arrival time - Required time (since we want data to arrive after it is required)
clock adjust = 0 (since hold is analyzed at same edge)
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CLK
ASYNC
clock
recovery time
async_in
07/25/15 - page 50
removal time
Q
CLR
I/O Analysis
reg2
Tdata
PRE
FPGA/CPLD or ASSP
PRE
C
CLR
CLR
TCO
Tsu/Th
Tclk2
Data
Arrival
Path
*
L
OSC
Data
Required
Path
Path 2
Path 3
Path 4
Path 1 starts at an input port and ends at the data input of a sequential element.
Path 2 starts at the clock pin of a sequential element and ends at the data input
of a sequential element.
Path 3 starts at the clock pin of a sequential element and ends at an output port.
Path 4 starts at an input port and ends at an output port.
07/25/15 - page 52
Register to Register
Input port to Register
Set the data arrival time at the port
Register to Output port
Set the port external delay
Input port to Output port
Input to Reg
Reg to Reg
IN_1
OUT_1
FF1
IdlClk
FF2
IN_2
Reg to Output
Input to Output
OUT_2
D Q
Setup
Time
_
C Q
_
C Q
Clock Period
Input Delay
Clock to Q
D Q
_
C Q
Clock
Root
Comb1
Gate +
Wire delay
D Q
Comb2
Setup
Time
_
C Q
Clock Period
Outside World
External Delay
Clock to Q
D Q
_
C Q
D Q
Comb1
Gate +
Wire delay
Setup
Gate + Time
_
C Q
Wire delay
0 Clock
Root
Clock Period
Input delay and output delay are set with respect to a clock
Default single-cycle
Setup requirement:
Comb delay < clock period - input delay - external delay
Hold requirement:
Comb delay > clock period - input delay - external delay
Combinational paths have no clocks defined for the module
Setup requirement:
Comb delay =< (delay set with set_path_delay_constraint -late) input_delay -external_delay
Hold requirement:
Comb delay >= (the delay set with set_path_delay_constraint -early)
- input_delay - external_delay
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The Header
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Lab Session 2
R: Cell delay when Output pin transitions from 0->1
F: Cell delay when Output pin transitions from 1->0
(i)
(ii)
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Lab Session 3
Delays given are :
U1 = 1.1 ns, U2 = 1.1 ns, U3 = 1 ns, U4 = 0.11ns, U5 = 0.11ns
Clk2Q = 0.5 ns max, 0.4 ns min, Tsu = 0.21ns
TH= 0.1ns
Calculate (i) Data Arrival Time for setup, (ii) Data Required time for setup,
(iii) Setup Slack, i.e. is setup timing met? (iv) Data Required time for
Hold, (v) Hold Slack, i.e. is hold timing met?
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Lab Session 4
Perform Setup/Hold Analysis for the following circuitry and report slack. If
there are any timing violations, suggest fixes that can be done on the
circuit so that the circuit operates within the stated timing objective.
Frequency of CLK = 100 MHz
Setup time of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 2 ns
Hold time of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 1 ns
Clock to Q delay of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 300 ps.
Propagation delay of Buffers in the library (B1, B2, B3, B4, B5 etc) is 500
ps.
Propagation delay of 2:1 Mux in the library (M1 etc) from input IN1/IN2
to OUT is 1 ns.
Propagation delay of 2:1 Mux in the library (M1 etc) from input SEL to
OUT is 500 ps.
Assume all net delays as zero.
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07/25/15 - page 65
Lab Session 5
For the circuit shown below, find the maximum frequency of CLK? Also
draw the output waveform of SIGA for input CLK at the maximum
frequency.
Setup time of D Flip-Flop (D-FF) = 2 ns
Hold time of D Flip-Flop (D-FF) = 1 ns
Clock to Q delay of Flip-Flop (D-FF) = 500 ps.
Propagation delay of the Invertor (I1) = 500 ps.
Assume all net delays as zero.
07/25/15 - page 66
Lab Session 6
In the circuit given below what is the maximum delay allowed in the combo
cloud to operate the circuit at 100MHz.
Clk to Q of Flop = 1ns
Flop Setup Time = 700ps
Flop Hold Time = 300ps
(Assume Wire Delays and Inverter Delay I1 are Zero and the Duty cycle is
50%)
07/25/15 - page 67
Lab Session 7
Compared to Figure 1 In Figure 2 FF2 Setup margin increased and Hold margin increased
b) Compared to Figure 1 In Figure 2 FF2 Setup margin decreased and hold margin increased
c)
Compared to Figure 1 In Figure 2 FF2 Setup margin decreased and hold margin decreased
d) Compared to Figure 1 In Figure 2 FF2 Setup margin increased and hold margin decreased
Ans: (b)
a)
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Summary
07/25/15 - page 69
Bibliography
https://solvnet.synopsys.com/
http://vsbu.wipro.com/Rep/Trainings/ASIC/vsbu24/VSBU24_Static_Timi
ng.ppt
http://vsbu.wipro.com/Rep/Trainings/ASIC/implementerTrg/articles/oth
ers/STA001_timing_basics.ppt
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