HYBRID MEMORY CUBE

Guided By
Mr.NISHANTH
Dept. of ECE

Present By
RAHUL NADH
EC7
No:59

CONTENTS
Introduction
Random access memory(RAM)
Currently using RAMs
Problems with existing technologies
The Hybrid Memory Cube
HMC Architecture
Through Silicon Via (TSV) Technology
Processor memory interaction
Memory technology comparison
Advantages
Disadvantages
Conclusion

INTRODUCTION
Nowadays we uses multi-core processors in computers for
better performance. DRAM technology has been utilized
as main memory in microprocessor-based systems for
decades. Multi-core processor performance is limited by
memory system bandwidth. The Hybrid Memory Cube is a
new memory technology which have three-dimensional
DRAM architecture that improves latency, bandwidth,
power and density.

RANDOM ACCESS MEMORY(RAM)

The RAM can be both read and, written, and is used to
hold the programs, operating system, and data required
by a computer system.

CLASSIFICATION OF RAM
RAM
DRAM

SRAM

ASYNCHRONOUS

SYNCHRONOUS

DDR4

RDRAM
DDR3

DDR SDRAM
DDR2

DDR1

CURRENTLY USING RAMS

1)DDR2
DDR2 is the next generation of memory developed after DDR
DDR2 is a 240 pin DIMM design that operates at 1.8 volts.
Has pre fetch buffer size 4 bits.
Starting in 2004, DDR2 was launched for use in desktops,
servers, notebooks, telecommunications/networking and other
platforms.
The maximum memory bandwidth of DDR2 is 5.34 GB/sec at
800MHz operating frequency

CURRENTLY USING RAMSContinue..

2)DDR3
DDR3 was the next generation memory introduced in the
summer of 2007 as the natural successor to DDR2.
DDR3 increased the pre-fetch buffer size to 8-bits
voltage level is lowered to 1.5 V.
The physical DDR3 is also designed with 240 pins
The maximum memory bandwidth of DDR2 is 10.66 GB/sec
at 800MHz operating frequency.

PROBLEMS WITH EXISTING

TECHNOLOGIES
Latency (memory wall)
Bandwidth related issues
Power / energy
Multi-core processors generate higher random request rates
Memory capacity per unit footprint
Scalability of bandwidth, densities, request rates and lower
latencies

THE HYBRID MEMORY

CUBE
Micron's Hybrid Memory Cube features a stack of
individual DRAMs connected by vertical pipelines
or vias.
IBMs new 3-D manufacturing technology TSV
used to connect the 3D micro structure.
The memory bandwidth is above 128 GB/Sec.
For HMC, Area needed for
1GB is 2.56mm2 .
For DDR3, area needed for
1GB is 294mm2 .

HMC ARCHITECTURE
For
For optimized
optimized
management
management of
of refresh,
refresh,
Self
Self test,
test, error
error detection
detection
and
and correction
correction

DRAM
LAYERS

VERTICAL
SLICES

LOGIC BASE

HMC ARCHITECTURE
Continue..
Logic

base contains control and

access circuits built in the memory
module.
Wide ,high-speed local bus for data
movement.
Advanced memory control provides
DRAM control at memory rather than
distant the processor.
Crossbar switch activates desired
memory location.

DRAM ARRAY & ACCESS

SINGLE DRAM CELL

SIMPLE 4X4 DRAM ARRAY

Bit line
Transistor
Word line

Capacitor

DRAM cell is made up of a single MOS

transistor and a storage capacitor.
The memory cell is written to by placing
a 1 or 0 charge into the capacitor
cell.
This charge, leaks off the capacitor due
to the sub-threshold current of the cell
transistor.
The charge must be refreshed several
times in each second.
Data I/O

HOW A MEMORY LOCATION IS

ACCESSED IN HMC?
CPU sends address, control signals and clock to the logic
base of HMC through the high speed link.
The memory map in the memory controller decodes the
memory address into (layer, bank, row & column).
The crossbar switch activates the desired memory location.
Command generator generates commands for the target
memory(activate ,read ,write ,pre charge ,refresh ).
The requested location is copied to the row buffer of the
selected bank (memory read).
The requested location of the selected bank is written by
data in the row buffer (memory write).

THROUGH SILICON VIA (TSV)

TECHNOLOGY
Through-Silicon-Via

(TSV) is the enabling technology

for the 3D integration of multiple dies into a single
stack.
Provide vertical electrical connectionsfrom the
active side to the backside.
Provides much higher input/output density than wire
bonding.
Inductive losses reduces.
Consume less power.

TSV PROCESS AND

INTEGRATION
1)VIA Creation
Deep reactive ion etch technology is used.
2)VIA Etching
VIAS are etched during or after back end of line processing
from the front side of full thickness wafer or backside of a
thinned wafer. Size of etched VIA is 10-25 micrometer.
3)VIA Liners
To avoid shorting to the silicon, the etched VIAS are lined with
insulating layer. CVD is used.
4)Depositing barrier layer
For chemically isolate semiconductor from soft metal
interconnect. Titanium and Tantalum are used as barrier
materials.

TSV PROCESS AND

INTEGRATION-continue..
5)VIA Fill
Done by using Copper
electroplating
6)Remove oxide and metal
Chemical mechanical polishing is
used.

Types of process sequences

MEMORY TECHNOLOGY
COMPARISON
Technology

VDD(V)

IDD(mA)

BW(GB/s)

Power
(mW/GB/s)

DDR1
(1GB Module)

2.5

2.19

2.66

2057.06

DDR2
(2GB Module)

1.8

2.88

5.34

971.51

DDR3
(2GB Module)

1.5

3.68

10.66

517.63

HMC
(4GB Module)

1.2

9.23

128

86.53

ADVANTAGES
Higher bandwidth
Higher signaling rate
Lower energy per useful unit of work done
Lower system latency
Increased request rate, for many-core
Higher memory packing density
Scalability for higher future bandwidths and density
footprint

DISADVANTAGES
Cost is high (30%higher than DDR3)
Designing is complex.
Manufacturing issues.
Need new motherboard form factor.

CONCLUSION
Hybrid

Memory Cube is a game changer, finally

giving architects a flexible memory solution that
scales bandwidth while addressing power efficiency
Through collaboration with IBM, Micron will provide
the industry's most capable memory offering
The goal is to get the first 3D chip modules to
market by 2013.

REFERENCES
www.hybridmemorycube.org
www.techonicals.com
www.en.wikipedia.org
www.engineering.com
www.ieeexplore.org
www.google.com

Any doubts???