Sequential circuit

the output of a combinational circuit depends solely upon the

input - no memory.
In order to build sophisticated digital logic circuits we need
circuits that have memory whose output depends upon both the
input of the circuit and its previous state
It is possible to produce circuits with memory using the digital
logic gates with the concept of feedback.

Latches and flip-flops

Gates are the building blocks of combinatorial
circuits, latches and flip-flops are the building
blocks of sequential circuits.
Gates had to be built directly from transistors latches can be built from gates, and flip-flops can be
built from latches.
Both latches and flip-flops are circuit elements
whose output depends not only on the current
inputs, but also on previous inputs and outputs.
The difference between a latch and a flip-flop is that
a latch does not have a clock signal, whereas a flipflop always does.

Latches
How can we make a circuit out of
gates that is not combinatorial? The
answer is feed-back, which means
that we create loops in the circuit
diagrams
If such feed-back is positive then the
circuit tends to have stable states,
and if it is negative the circuit will
tend to oscillate

RS Latch using NAND gate

The circuit shown below is a basic NAND latch.
The inputs are "S" and "R" for "Set" and "Reset" respectively.

Input

Output
State

R'

S'

Q'

Indeterminate

Reset

Set

NC

NC

No Change

Operation:
Case 1: If S=1, R=0, it will reset the RS latch Q=0 and Q=1
Case 2: If S=0, R=1, it will set the RS latch Q=1 and Q=0
Case 3: If S=R=1, the latch will remain in previous state
Case 4: If S=R=0, the latch is unpredictable

RS Latch using NOR gate

The circuit shown below is a basic NOR latch.

The inputs are "S" and "R" for "Set" and "Reset" respectively.

Input

Output

State

Q'

NC

NC

No Change

Set

Reset

Operation:
Case 1: If S=1, R=0, it will set the RS latch Q=1 and Q=0
Case 2: If S=0, R=1, it will reset the RS latch Q=0 and Q=1
Case 3: If S=R=1, the latch is unpredictable
Case 4: If S=R=0 No Change in the latch

Indeterminate

Flip-flops
Latch is an asynchronus circuit change in input is
transmitted to the output Q and Q
Operation of the latch can be modified by a control
input called Clock or clock pulse
Clock with latch is called flip-flop working as a
synchronous version
Binary storage device stores binary bit 2 stable
states HIGH & LOW
Change the operation of the circuit depending on the
state of one or more Flip flops

Types of Flip-Flops

Flip-Flops
can
be
classified
according to the number of inputs
they possess and the manner in
which they affect the binary state of
the flip-flop.
SR type Flip-flop or Set / Reset
T type Flip-flop or Triggered /Toggle
D type Flip-flop or Data / Delay
JK type Flip-flop

SR Flip-flop - (Set / Reset)

Basic Symbol of the Clocked RS Flip flop ig given in figure 1
Logic diagram (figure 2) reviews that it consists of basic
NOR Latch circuit and 2 AND gates at the input.
Clock = 0 ----AND gate = 0 ----circuit remains in same state
Clock = 1 ----Input from AND gate reaches RS Latch
Works as basic RS Latch
Case 1: R=0 and S=0
Output of AND gate = 0
If Q=1 and Q=0 Output of 1st NOR gate =1 and 2nd gate =0
Hence No change state
Case 2: R=1 and S=0
Output of 1st AND gate = 1 and 2nd =0
Output of 1st NOR gate =0 and 2nd gate =1
Hence Reset state

Case 3: R=0 and S=1

Output of 1st AND gate = 0 and 2nd =1
Output of 1st NOR gate =1 and 2nd gate =0
Hence Set state

Case 4: R=1 and S=1

Output of both AND gate = 1
Output of both NOR gate =0
Hence Indeterminate state

D Flip-Flop
FF whose output follows it data input when the clock is
The D flip-flop is a modification of the clocked SR flipflop.
The D input goes directly into the S input and the
complement of the D input goes to the R input.
If D=1, the flip-flop is switched to the set state (unless it
was already set). If it is 0, the flip-flop switches to the
Reset state

JK Flip-Flop

(Jack Kilby)

indeterminate state of the SR type is

defined (refined) in the JK type
Toggle: alternate between opposite binary
states with each applied clock pulse
Inputs J and K behave like inputs S and R
to set and clear the flip-flop (J - set and K clear)
When logic 1 inputs are applied to both J
and K simultaneously, the flip-flop
switches to its complement state, ie., if
Q=1, it switches to Q=0 and vice versa.

Case 1: J=K=0
Both AND gates are disbled
CP no effect
Hence No change state

Case 2: J=0 and K=1

1st AND gate is disabled i.e., S=0 and R=1
Hence Reset state

Case 3: J=1 and K=0

2nd AND gate is disabled i.e., S=1 and R=0
Hence Set state

Case 4: J=K=1 possible to Set/Reset

Q=High 2nd AND gate is Reset and vice-versa
Hence Toggle (Opposite) state

T Flip-Flop
T flip-flop is obtained from the JK type if both inputs are tied
together (i.e J=K always)
CP=0 Both AND gate = 0 No change State
CP=1; T=0;
Both AND gate = Disable No change State
CP=1; T=1;
Both AND gate depend on previous output & finally toggles