Microcontrollers

(8051)

Microprocessors:
General-purpose microprocessor
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example Intels x86, Motorolas 680x0

CPU
GeneralPurpose
Microprocessor

Many chips on mothers board

Data Bus

RAM

ROM

I/O
Port

Address Bus
General-Purpose Microprocessor System

Timer

Serial
COM
Port

Microcontroller :
A smaller computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU
I/O
Port

RAM ROM
Serial
Timer COM
Port

A single chip
Microcontroller

Microprocessor vs. Microcontroller

Microprocessor
CPU is stand-alone,
RAM,
ROM, I/O, timers are separate
designer can decide on the
amount of ROM, RAM and I/O
ports.
expansive
versatility
general-purpose

Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
for applications in which cost,
power and space are critical
single-purpose

Advantages over
Microprocessor

Cost is lower
Standalone microprocessor never used

memory, I/O, clock necessary

For microprocessor- large size PCB
Large PCB- more effort and cost
Big physical size
More difficult to trouble shoot mp based
A microcontroller is a microprocessor with
integrated peripherals.

Advantages of
Microcontroller

Low cost
Small size of product
Easy to troubleshoot and maintain
More reliable
Additional memory, I/O can also be added
Software security feature
All features available with 40 pins.
Useful for small dedicated applications and not

for larger system designs which may require

many more I/O ports.
Mostly
used to implement small control
functions.

Block Diagram
External interrupts
Interrupt
Control

On-chip
ROM for
program
code

Timer/Counter

On-chip
RAM

Timer 1
Timer 0

CPU

OSC

Bus
Control

4 I/O Ports

P0 P1 P2 P3

Address/Data

Serial
Port

TxD RxD

Counter
Inputs

 Accumulator (ACC):-

Acts as an operand register, in case of some instructions.

This may be either implicit or specified in the instruction.
SFR register.
B :- used to store one of the operands for multiply and
divide instructions.
SFR register.
PSW:- set of flags contain the status information. SFR
register.
SP:- Incremented before data is stored onto the stack
using push and call instructions.
Contains 8-bit stack top address.
After reset, SP is initialized to 07.
Stack is defined any where in the on-chip 128-byte RAM.
SFR register.

 DPTR:- 16- bit register contains a higher byte (DPH) and lower byte (DPL) of

a 16-bit external data RAM address.

SFR register.
Port 0 to 3 Latches and Drivers:four latches and driver pairs are allotted to each of the four on-chip I/O ports.
Identified as P0,P1,P2, and P3.
User can communicate with these ports using the addresses allotted to them
on SFR.
Serial Data Buffer:SBUF
Internally contains two independent registers.
Transmit buffer which is parallel-in serial-out register.
Receive buffer which is serial-in parallel-out register.
Loading a byte to the transmit buffer initializes serial transmission of that
byte.
If a byte is written to SBUF, it initiates serial transmission and if the SBUF is
read, it reads the received serial data.
SFR register.

 Timer Registers:-

Two 16-bit registers can be accessed as their lower and

upper bytes.
TL0,TH0, TL1, and TH1.
SFR registers.

Control Registers:-

IP, IE, TMOD, TCON, SCON and PCON contain control and
status information for interrupts, timers/counters and serial
port.
SFR registers.

Timing and Control Unit:-

Derives all the necessary timing and control signals

required for the internal operation of the operation and
also signal for controlling the external system bus.
Oscillator:- generates the basic timing clock signal for

the operation of the circuit using crystal oscillator.

Instruction Register:

Decodes the opcode of an instruction to be executed and

gives information to the timing and control unit to
generate necessary control signals for the execution of
the instruction.
EPROM and Program Address Register:-

These blocks provide an on-chip EPROM and a

mechanism to internally address it.
EPROM is not available in all 8051 versions.
RAM and RAM Address Register:Provide 128 bytes of RAM and a mechanism to address it
internally.
ALU:- performs 8-bit arithmetic and logical operations

over the operands held by the temporary registers

TMP1 and TMP2.
SFR Register Bank:- set of special function registers,
which can be addressed using their respective
addresses which lie in the range 80H to FF H.

Pin Description of the 8051

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051
(8031)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

Signal Description of 8051:RESET:- resets the 8051, only when it goes high for

two or more machine cycles.

ALE/PROG:- ALE output pulse indicates that the
valid address bits are available on their respective
pins. ALE signal is valid only for external memory
accesses.
ALE pulses are emitted at a rate of one-sixth of the
oscillator frequency.
This pin acts as program pulse input during on-chip
EPROM programming. ALE may be used for external
timing or clocking purpose. One ALE pulse is skipped
during each access to external data memory.

 EA*/Vpp

:- If tied low, indicates that the 8051 can address external

program memory.
PSEN* :- Program store enable is an active-low output signal that acts as a

strobe to read the external program memory. Goes low during external
program memory accesses.
Port 0(P0.0- P0.7) :-

8-bit bidirectional bit addressable I/O port.

Acts as a multiplexed address/data lines during external memory accesses,
i.e. when EA* is low and ALE emits a valid signal.
Port 0 receives code bytes during programming of internal EPROM.
Port 1(P1.0- P1.7) :- acts as an 8-bit bidirectional bit addressable port.
Port 2(P2.0- P2.7) :- acts as 8-bit bidirectional bit addressable I/O port.

During external memory accesses, port 2 emits higher eight bits of address
(A8-A15) which are valid, if ALE goes high and EA is low.
Port 3(P3.0- P3.7) :- acts as 8-bit bidirectional bit addressable I/O port.
Also serve the alternate functions

Signal Description of 8051:XTAL1 and XTAL2: Inbuilt oscillator which derives the necessary clock
frequency for the operation of the controller.
XTAL1 is the input of the amplifier and XTAL2 is the output
of the amplifier.
Crystal is connected externally between these two pins to
complete the feed back path to start oscillations. The
controller can be operated on an external clock.

Register Set of 8051

Special Function Registers (SFR) are special

purpose registers 21 in number

Addresses from 80H to FF H of all SFRs
Two 8 bit registers. A and B store operands
A, B, PSW, P0-P3, IP, IE, TCON,SCON
Bit addressable, 8bit each, 11 in number

SP, DPH,DPL,TMOD,TH0,TL0,TH1,TL1,SBUF,PCON
Byte addressable, 8bit each.
DPTR data pointer, accesses external. memory. DPH + DPL
= DPTR
Starting 32 bytes of RAM general purpose register,

divided into 4 register banks of 8 registers each.

Only one of these bank accessible at one time.
RS1 and RS0 of PSW used to select bank.

Register Set of 8051

TH0-TL0 and TH1-TL1
16 bit timer registers
P0-P3 port latches
SP, PSW, IP Interrupt Priority, IE enable
TCON timer/counter control registers to turn

on/off the timers, interrupt control flags for

external. interrupt like INT1 and INT0
TMOD modes of operation of timer/counter
SCON serial port mode control register
SBUF serial data buffer for transmit and receive
PCON Power control register power down bit,
idle bit

Registers
A
B
R0

DPTR

DPH

DPL

R1
R2

PC

PC

R3
R4

Some 8051 16-bit Register hold addresses

R5
R6
R7
PSW (8)
Some 8-bit Registers of the 8051

SP (8)

8051 features
Internal ROM 4K, RAM 128bytes
Thirty two I/O pins arranged as 4 8 bit ports P 0 P3
Two 16 bit timer/counters T0 and T1

Full duplex serial data receiver/transmission

using SBUF
Control registers TCON, TMOD, SCON, PCON, IP

and IE
Two external and three Internal Interrupt sources
Oscillator and clock circuits

Two power saving modes:1.

Idle mode
2.
Power down mode
Idle Mode:Oscillator continues to run, the interrupt, serial port, and timer blocks
are active but the clock to the CPU is disabled.
CPU status is preserved.
Terminated with a hardware interrupt or hardware reset signal.
After this, the CPU resumes program execution from where it left off.
Power down Mode:on-chip oscillator is stopped.
All functions of the controller are held maintaining the contents of
RAM.
only way to terminate this mode is hardware reset.
Reset redefines all the SFRs but the RAM contents are left unchanged.
Both these modes can be entered by setting the respective bit in an
internal register called PCON register using software.

Counter and Timers:Applications require counting of external events-

frequency of a pulse train, or the generation of

internal time delay between computer actions.
Accomplished using software techniques.
Two 16-bit up counters, named T0 and T1 for
general use of the programmer.
May be programmed to count internal clock pulses,
acting as timer, or to count external pulses as a
counter.
Counters are divided into two 8-bit registers called
timer low(TL0,TL1) and Timer high (TH0, TH1).
Controlled by TMOD, TCON and certain program
instructions.

Counter and Timers:-

Counter :Counters have been included on the chip to

relieve the processor of timing and counting

tasks.
To count number of internal pulses or external
events, a number is placed in one of the
counters- maximum count less the desired
count, plus 1.
Counter increments from the initial number to
maximum and then roll over to 0 on the final
pulse and also sets a timer flag.
The flag condition may be tested or may be used
to interrupt the program.

Timer :If a counter is programmed to be a timer, it will count the

internal clock frequency of the 8051 oscillator divided by

12d.
The resultant timer clock is gated to the timer by means of
cirucit.
In order for oscillator clock pulses to reach the timer, C/T*
bit in the TMOD register must be set to 0(timer operation).
Bit TRx in the TCON register must be set to 1(timer to run),
and the gate bit in TMOD register must be 0, or external
pin INTX* must be 1.
The counter is configured as a timer, then the timer pulses

are gated to the counter by the run bit and the gate bit or
the external input bits INTX*.

Timer Modes of Operation:Operate in any one of four modes.

Determined by the mode bits, M1, M0 of

register.

TMOD

Timer Mode 0:Setting timer x bits to 0 0 in the TMOD .

THx as an 8-bit counter and TLx as a 5-bit

counter.
Pulse input is divided by 32d in TL so that TH
counts the original oscillator frequency reduced
by a total 384d.
Timer flag is set whenever THx goes from FF H
to 00 H, or in 0.0164 seconds for a 6 MHz crystal
if THx starts at 00H.

Timer Mode 1:Similar to Mode 0 except TLx is configured as full

8-bit counter.
Mode bits are set to 0 1 in TMOD.
Timer flag would be set in 1311 seconds using a
6 MHz crystal.

Timer Mode 2:Setting the mode bits 1 0

in TMOD configures
the timer to use only the TLx counter as an 8-bit
counter.
THx is used to hold a value that is loaded into
TLx every time TLx overflows from FF H to 00 H.
Timer flag is also set when TLx overflows.
Exhibits an auto-reload feature: TLx will count up
from the number in THx, overflow, and be
initialized again with the contents of THx.

Timer Mode 3: Timers 0 and 1 may be programmed to be in mode 0,1 or 2

independently of a similar mode for the other timer.

The timers do not operate independently if mode 3 is chosen for
timer 0.
Placing timer1 in mode 3 causes it to stop counting; the control
bit TR1 and the timer 1 flag TF1 are then used by timer 0.
Timer 0 in mode 3 becomes two completely separate 8-bit
counters.
TL0 is controlled by the gate arrangement of timer/counter
control logic and sets timer flag TF0 whenever it overflows from
FF H to 00 H. TH0 receives the timer clock under the control of
TR1 only and sets the TF1 flag when it overflows.
Timer1 may still be used in modes 0,1, and 2, while timer 0 is in
mode 3 with one important exception: No interrupts will be
generated by timer 1 while timer 0 is using the TF1 overflow flag.
Switching timer 1 to mode 3 will stop it(and hold whatever count
is in timer1).

Counting: Difference between counting and timing is the source of the clock

pulses to the timers.

When used as a timer, the clock pulses are sourced from the
oscillator through the divide-by-12d circuit. When used as a
counter, pin T0(p3.4) supplies pulses to counter 0, and pin T1
(p3.5) to counter 1. The C/T* bit in TMOD must be set to enable
pulses from the Tx pin to reach the control circuit.
The input pulse on Tx is sampled during P2 of state 5 every
machine cycle. A change on the input from high to low between
samples will increment the counter.
Each high and low state of the input pulse must thus be held
constant for at least one machine cycle to ensure reliable counting.
Since this takes 24 pulses, the maximum input frequency that can
be accurately counted is the oscillator frequency divided by 24. For
our 6 MHz crystal, the calculation yields a maximum external
frequency of 250KHz.

Memory Addressing
Total memory logically divided into program

and data memory.

Program memory - EPROM

Program code
4KB internal from 0000 0FFFH
64KB external under the control of PSEN*, till

FFFFH
Internal external memories are distinguished by
PSEN* signal.
In ROM-less version of 8051 PSEN* used to
access external memory

Memory Addressing:Data Memory RAM (read from or written to)

Intermediate results, variables, const
64KB of external with DPTR signal
Generates RD* and WR* signal during external

memory access.
Internal data memory two parts - 128 bytes
Internal RAM and secondly set of addresses from
80-FF H for SFRs
128 bytes from 00 7FH are addressed using
direct or indirect
SFR addresses
(80 FF H) only direct
addressing mode

Memory Addressing
Lower 128 bytes in three sections
00-1F

32 bytes 4 banks 00,01,10,11 each

containing 8 registers of 8 bits each. Only one
accessible at a time with PSW selection bits.
20-2FH 16bytes is bit addressable with
addresses 00 to 7FH.
accessed with bit number is directly
specified or bit is mentioned with its position.
20.7 or 20.0, or 0-7
30-7F 80 bytes of general purpose data
memory. It is byte addressable, used for stack

 RAM memory space allocation in the 8051

External I/O interfacing

8051 has two timers, one Serial I/O port

and 4 8bit addressable ports.

Some Applications require additional I/O
devices to be interfaced with 8051.
Such external I/O devices are interfaced
with 8051 as memory -mapped I/O devices.
I/O devices are treated as external memory
locations, as they consume external
memory addresses.

Interrupts of 8051
Provides five sources of Interrupts.
INT0 * and INT1* are two external interrupt

inputs
These are processed internally by IE0 and IE1 flags

Two timers which generate interrupt when FFFFH

Serial port interrupt if RI or TI is set.

Single step interrupt by software

All these interrupts are enabled using a IE.

Priorities are programmed using IP.

Serial Data Input/Output: Cost effective way to communicate is to send and receive

data bits serially.

8051 has a serial data communication circuit that uses the
register SBUF to hold data.
SCON controls data communication, PCON controls data
rates, and pins RXD(p3.0) and TXD (p3.1) connect to the
serial data network.
SBUF contains two registers. TXD, RXD. Both are mutually
exclusive registers use address 99H.
Four modes for serial data communication that are chosen
by setting the SMX bits in SCON. Baud rates are
determined by the chosen mode.

Serial Data Interrupts: Slow process, occupying many milliseconds per data byte

to accomplish.
Serial data flags are available in SCON to aid in efficient
data transmission and reception.
Transmission is under the control of program, but the
reception is unpredictable.
TI and RI are set in SCON whenever a byte is transmitted
is or received.
The program must read these flags to determine which
caused the interrupt and then clear the flag.

Data Transmission: Transmission of serial data bits begins anytime data is

written to SBUF.
TI is set to a 1 when the data has been transmitted and
signifies that SBUF is empty.
If the program fails to wait for the TI flag and overwrites
SBUF while a previous data byte is in the process of being
transmitted, the results will be unpredictable.

Data Reception: Reception

of data will begin if the receive enable bit

(REN) in SCON is set to 1 for all modes. For mode 0 only,
RI must be cleared to 0.
RI flag is set after data has been received in all modes.
Reception can begin in modes 1,2, and 3 if RI is set when
the serial stream of bits begins. RI must have been reset
by the program before the last bit is received or the
incoming data will be lost.
Incoming data is not transferred to SBUF until the last data
bit has been received so that previous transmission can be
read from SBUF while the new data is being received.

Serial Data Transmission

Four Modes- provide variety of ways and multitude
Modes:baud rates.

of

Modes are selected by the mode bits SM0 and SM1 in

SCON.
Baud rates are fixed for mode 0 and variable using timer1
and the SMOD bit in SCON for modes 1,2 and 3.

Serial Data Mode 0- shift

register
mode
:-in SCON are set to 0 0.

Mode bits SM0

and SM1
Configures SBUF to transmit or receive 8-bits using pin

RXD.
TXD is connected to the internal shift frequency pulse to
supply shift pulses to external circuits.
Baud rate is fixed at 1/12 of the oscillator frequency, the
same rate is used by the timers when in the timer
configuration.
TXD shift clock is a square wave that is low for machine
cycle states s3-s4-s5 and high for s6-s1-s2.
When transmitting, data is shifted out of RXD, the data
changes on the falling edge of s6p2, or one clock pulse
after the rising edge of the output TXD shift clock.

Data Transmission: Transmission of serial data bits begins anytime data is

written to SBUF.
TI is set to a 1 when the data has been transmitted and
signifies that SBUF is empty.
If the program fails to wait for the TI flag and overwrites
SBUF while a previous data byte is in the process of being
transmitted, the results will be unpredictable.

Data Reception: Will begin if the receive enable bit (REN) in SCON is set to 1 for

all modes.
In addition, for mode 0 only, RI must be cleared to 0.
Receiver Interrupt flag RI is set after data has been received in
all modes. Setting REN is the only direct program control that
limits the reception of unexpected data; the requirement that
RI also be 0 for mode 0 prevents the reception of new data
until the program has dealt with the old data and reset RI.
Reception can begin in modes 1,2 and 3 if RI is set when the
serial stream of bits begins. RI must have been reset by the
program before the last bit is received or the incoming data will
be lost. Incoming data is not transferred to SBUF until the last
data bit has been received so that the previous transmission
can be read from SBUF while the new data is being received.

TMOD Register:

Gate :

When set, timer only runs while INT(0,1)

is high.

C/T : Counter/Timer select bit.

M1 : Mode bit 1.
M0 : Mode bit 0.

TCON Register:

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit.
TF0: Timer 0 overflag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag.
IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag.
IT0: External interrupt 0 type flag.

Memory addressing

Program memory - EPROM

Intermediate results, variables, const

4KB internal from 0000 0FFFH
64KB external with PSEN, till FFFFH
Internal external difference PSEN

Data Memory RAM

64KB of external with DPTR signal
Internal memory two parts - 128 bytes Internal RAM

and secondly set of addresses from 80-FFH for SFRs

128 bytes from 00 7FH direct or indirect
SFR addresses only direct addressing mode

Memory Addressing
Lower 128 bytes in three sections
00-1F 32 bytes 4 banks 00,01,10,11 each

containing 8 registers of 8 bits each. Only

one accessible at a time with PSW bits.
20-2FH 16bytes is bit addressable with
addresses 0F to 7FH, 20.7 or 20.0, or 0-7
30-7F 80 bytes of general purpose data
memory. It is byte addressable, used for
stack

 RAM memory space allocation in the 8051

External I/O interfacing

8051 has two timers, one Serial i/o port and

4 8bit addressable ports.

More I/O as external memory-mapped I/O

Interrupts of 8051
5 sources of Interrupts
INT0 and INT1 bars external interrupt inputs
These are processed internally by IE0 and IE1 flags
Two timers which generate int when FFFFH
Serial port interrupt if R1 or T1 is set.

Single step int by software

Interrupt Enable Register :

EA
---

: Global enable/disable.
: Undefined.

ET2 :Enable Timer 2 interrupt.

ES :Enable Serial port interrupt.
ET1 :Enable Timer 1 interrupt.
EX1 :Enable External 1 interrupt.
ET0 : Enable Timer 0 interrupt.
EX0 : Enable External 0 interrupt.

Addressing modes
Direct - MOV R0, 89 H, Eg 89 of TMOD
operands 8 bit address field
Internal data RAM and SFRS only
Indirect - ADD A, @ R0
Address is stored in R0 or R1 or SP if 8bits
16 bit addresses only in DPTR

Register Instructions - ADD A, R7

Operands in R0 R7 of selected register bank.
Register bank selected by two bank select bits of PSW
Register specific (Register Implicit) RLA
Immediate Mode ADD A, #100
Indexed Addressing

Addressing Modes
Indexed Addressing
MOVC A, @A+DPTR
JMP @ A + DPTR
Used to access only program memory not data
Used for look up table manipulations
Only PC or data pointer 16 bit storage registers

allowed
Base address in PC or DPTR, relative addr in A

Identify the addressing

modes
MOV A,#50H
MOV A, R5
MOV DPTR,#nn
MOV 90H, #0a5H
MOV 0A8H, 77H
MOV @R1,#n
MOV A, @R0
MOVX @DPTR,A
MOVC A, @A+PC

 Explain the internal and external program memory as well as data

memory of 8051 with the diagram showing their capacities.

Draw the diagram to Interface Program memory of 16K x 8 EPROM to
8051and give its memory map. The address of memory map should
start from 0000H.
Discuss about various addressing modes of 8051.
Explain the interrupt structure. Mention the priority. Explain how least
priority is made as highest priority?
Explain in 8051 instruction set to handle bit addressable RAM.
Draw and discuss the formats and bit definitions of the following SFRs .
(a) IP(b) TMOD(c) TCON(d) SCON
(a) Explain the internal RAM organization of 8051? Discuss how
switching between register banks is possible?
What is the use of SFR? List out the SFR of 8051?
Discuss the advantages of microcontroller based systems over
microprocessor based systems?
(b) With a neat sketch discuss the internal architecture of 8051?
Explain the Flags d program status word of 8051 microcontroller?
Explain the different types of Interrupt in 8051.
Discuss the register set of 8051
Explain the addressing modes of 8051 microcontroller.
Explain the different modes of operation of timer/counter in 8051.
How does 8051 differentiate between the external and Internal prog
mem