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ARM

Advanced RISC Machines

Scan and JTAG Principles

ARM Advanced RISC Machines Scan and JTAG Principles Scan and JTAG Principles 1
ARM Advanced RISC Machines Scan and JTAG Principles Scan and JTAG Principles 1

Scan and JTAG Principles

ARM Advanced RISC Machines Scan and JTAG Principles Scan and JTAG Principles 1

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Module Contents

*

Scan Fundamentals

 

Full and partial scan techniques

Level sensitive and edge triggered methods

*

JTAG and the Test Access Port (TAP)

JTAG Interface Signals

Test Access Port Controller

Test Access Port Instructions

Module Contents * Scan Fundamentals • Full and partial scan techniques • Level sensitive and edge
Module Contents * Scan Fundamentals • Full and partial scan techniques • Level sensitive and edge

Scan and JTAG Principles

Module Contents * Scan Fundamentals • Full and partial scan techniques • Level sensitive and edge

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Scan Basics

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Flip-flop elements within a circuit can be connected serially to form a shift register structure.

*

Access to the scan chain data via 2 pins, Test Data In (TDI) and Test Data Out (TDO).

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Data can be applied serially on TDI to set up the system state, while state data can be read serially on TDO.

Scan Basics * Flip-flop elements within a circuit can be connected serially to form a shift
Scan Basics * Flip-flop elements within a circuit can be connected serially to form a shift

Scan and JTAG Principles

Scan Basics * Flip-flop elements within a circuit can be connected serially to form a shift

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Level Sensitive Scan Design

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2 basic design principles:

 

Master-slave gated flip-flops form the basic scan element.

Each register can be converted to form a serial shift register

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Advantages:

 

Hazard Free

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Disadvantages

Complexity (Size - speed).

Level Sensitive Scan Design * 2 basic design principles: • Master-slave gated flip-flops form the basic
Level Sensitive Scan Design * 2 basic design principles: • Master-slave gated flip-flops form the basic

Scan and JTAG Principles

Level Sensitive Scan Design * 2 basic design principles: • Master-slave gated flip-flops form the basic

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Serial Scan

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Uses edge triggered latches to form the scan element.

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Lower complexity; higher speed.

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Sensitive to clock skew.

*

May need synchronisation (redundant) opposite edge triggered scan elements to rectify.

Serial Scan * Uses edge triggered latches to form the scan element. * Lower complexity; higher
Serial Scan * Uses edge triggered latches to form the scan element. * Lower complexity; higher

Scan and JTAG Principles

Serial Scan * Uses edge triggered latches to form the scan element. * Lower complexity; higher

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ARM Scan Cell

Shift/Load G1 1 1D To next From last 1 cell cell C1 1D C1 G1 To
Shift/Load
G1
1
1D
To next
From last
1
cell
cell
C1
1D
C1
G1
To logic
From logic
1
1
or pin
or pin
Clock
Update
Mode
Scan and JTAG Principles
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Scan Nomenclature

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Full Scan

 

Connection of all flip-flop elements into a single serial shift register.

*

Partial Scan

 

Connection of a subset of all flip-flop elements to form a serial shift register.

There can be more than one partial scan chain.

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Boundary Scan

All I/Os are isolated from the core logic by a serial shift register.

This shift register can be used to apply system-level stimuli to the core serially.

Scan Nomenclature * Full Scan • Connection of all flip-flop elements into a single serial shift
Scan Nomenclature * Full Scan • Connection of all flip-flop elements into a single serial shift

Scan and JTAG Principles

Scan Nomenclature * Full Scan • Connection of all flip-flop elements into a single serial shift

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System Level Test

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Increasing board complxities and use of multichip modules has stretched traditional system test techniques.

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Joint Test Action Group (JTAG) to formulate a unified scan-based system test method.

*

Result was the IEEE 1149 Boundary Scan architecture.

System Level Test * Increasing board complxities and use of multichip modules has stretched traditional system
System Level Test * Increasing board complxities and use of multichip modules has stretched traditional system

Scan and JTAG Principles

System Level Test * Increasing board complxities and use of multichip modules has stretched traditional system

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JTAG System Test

TAP TAP Control Control TAP TDI TCK TMS TRST TDO
TAP
TAP
Control
Control
TAP
TDI
TCK
TMS
TRST
TDO
JTAG System Test TAP TAP Control Control TAP TDI TCK TMS TRST TDO Scan and JTAG
JTAG System Test TAP TAP Control Control TAP TDI TCK TMS TRST TDO Scan and JTAG

Scan and JTAG Principles

JTAG System Test TAP TAP Control Control TAP TDI TCK TMS TRST TDO Scan and JTAG

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Extra JTAG Logic

TAP Control
TAP
Control

Test Access Port (TAP)

Boundary-Scan

Test Registers and Decoder
Test Registers
and Decoder

Cell

Extra JTAG Logic TAP Control Test Access Port (TAP) Boundary-Scan Test Registers and Decoder Cell TAP
TAP Controller
TAP
Controller

Test Access Port (TAP)

Extra JTAG Logic TAP Control Test Access Port (TAP) Boundary-Scan Test Registers and Decoder Cell TAP

Package Pin

Extra JTAG Logic TAP Control Test Access Port (TAP) Boundary-Scan Test Registers and Decoder Cell TAP

Scan and JTAG Principles

Extra JTAG Logic TAP Control Test Access Port (TAP) Boundary-Scan Test Registers and Decoder Cell TAP

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TAP Pin Descriptions I

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Test Clock Input (TCK)

 

Independent of the system clock.

Rising edge used to load signals applied at the TAP input pins (TDI,TMS).

Falling edge used to clock data out of the TAP data output (TDO).

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Test Mode Select (TMS)

 

Test logic operation determined by input sequence on this pin.

In undriven state, TMS should be a logic 1.

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Test Data Input (TDI)

 

Serial test data applied at this input.

Again, should be pulled up to logic 1when undriven.

TAP Pin Descriptions I * Test Clock Input (TCK) • Independent of the system clock. •
TAP Pin Descriptions I * Test Clock Input (TCK) • Independent of the system clock. •

Scan and JTAG Principles

TAP Pin Descriptions I * Test Clock Input (TCK) • Independent of the system clock. •

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TAP Pin Descriptions II

*

Test Data Output (TDO)

 

Serial data out.

When there is no shift activity, TDO is set to a high-impedence state.

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Test Reset (TRST)

TAP controller can be initialised via TCK and TMS.

Optional TRST pin allows reset independently of TCK and TMS.

Pulling TRST to 0 asynchronously forces the test logic into its reset state.

TAP Pin Descriptions II * Test Data Output (TDO) • Serial data out. • When there
TAP Pin Descriptions II * Test Data Output (TDO) • Serial data out. • When there

Scan and JTAG Principles

TAP Pin Descriptions II * Test Data Output (TDO) • Serial data out. • When there

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TAP Architecture

Test Data Registers Device ID Register Bypass register Instruction Decode TDO Instruction Reg. TDI TAP TMS
Test Data Registers
Device ID Register
Bypass register
Instruction Decode
TDO
Instruction Reg.
TDI
TAP
TMS
Controller
TCK
nTDOEN
nTRST
  • 13

TAP Architecture Test Data Registers Device ID Register Bypass register Instruction Decode TDO Instruction Reg. TDI

Scan and JTAG Principles

TAP Architecture Test Data Registers Device ID Register Bypass register Instruction Decode TDO Instruction Reg. TDI

TAP Control State Machine

Test-Logic
Test-Logic
Reset TMS=0 TMS=1 TMS=1 TMS=1 Run-Test/Idle Select-DR-Scan Select-IR-Scan TMS=0 TMS=0 TMS=1 TMS=1 Capture-DR Capture-IR TMS=0 TMS=0
Reset
TMS=0
TMS=1
TMS=1
TMS=1
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
TMS=0
TMS=0
TMS=1
TMS=1
Capture-DR
Capture-IR
TMS=0
TMS=0
TMS=0
Shift-DR
Shift-IR
TMS=0
TMS=1
TMS=1
Exit1-DR
Exit1-IR
TMS=0
TMS=0
TMS=0
Pause-DR
TMS=0
Pause-IR
TMS=1
TMS=1
TMS=0
TMS=0
Exit2-DR
Exit2-IR
TMS=1
TMS=1
Update-DR
Update-IR
TMS=1
TMS=0
TMS=1
TMS=0

TMS=0

TMS=1

TMS=1

TMS=0

TAP Control State Machine Test-Logic Reset TMS=0 TMS=1 TMS=1 TMS=1 Run-Test/Idle Select-DR-Scan Select-IR-Scan TMS=0 TMS=0 TMS=1
TAP Control State Machine Test-Logic Reset TMS=0 TMS=1 TMS=1 TMS=1 Run-Test/Idle Select-DR-Scan Select-IR-Scan TMS=0 TMS=0 TMS=1

Scan and JTAG Principles

TAP Control State Machine Test-Logic Reset TMS=0 TMS=1 TMS=1 TMS=1 Run-Test/Idle Select-DR-Scan Select-IR-Scan TMS=0 TMS=0 TMS=1

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Controller States I

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TEST-LOGIC-RESET

 

Test logic disabled; allows for normal chip operation.

*

RUN-TEST-IDLE

 

Controller state between scan operations.

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SELECT-DR/IR-SCAN

 

Temporary controller states in which all test data registers selected by the current instruction retain their current state.

Initiates register scan sequence.

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CAPTURE-DR

The selected test data register captures its data inputs on the rising edge of TCK.

Controller States I * TEST-LOGIC-RESET • Test logic disabled; allows for normal chip operation. * RUN-TEST-IDLE
Controller States I * TEST-LOGIC-RESET • Test logic disabled; allows for normal chip operation. * RUN-TEST-IDLE

Scan and JTAG Principles

Controller States I * TEST-LOGIC-RESET • Test logic disabled; allows for normal chip operation. * RUN-TEST-IDLE

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Controller States II

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CAPTURE-IR

 

The instruction register loads a fixed bit pattern on rising TCK.

*

SHIFT-DR/IR

 

In these states the test data register (DR) or the instruction register (IR), shifts its data by one stage on each rising edge of TCK.

*

EXIT1-DR/IR

 

These are temporary controller states. If TMS = 1, then on the next rising TCK, the state machine will enter the Update-DR/IR states.

*

UPDATE-DR

 

Some test data registers have latched parallel outputs.

These outputs are latched on falling TCK

Controller States II * CAPTURE-IR • The instruction register loads a fixed bit pattern on rising
Controller States II * CAPTURE-IR • The instruction register loads a fixed bit pattern on rising

Scan and JTAG Principles

Controller States II * CAPTURE-IR • The instruction register loads a fixed bit pattern on rising

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Controller States III

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UPDATE-IR

 

On TCK falling the instruction shifted in during SHIFT-IR is latched into the instruction register.

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PAUSE-DR/IR

These states allow for the instruction/data shift operations to be halted temporarily.

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EXIT2-DR/IR

Temporary controller states allowing either resumption of or termination of the current scan instruction.

Controller States III * UPDATE-IR • On TCK falling the instruction shifted in during SHIFT-IR is
Controller States III * UPDATE-IR • On TCK falling the instruction shifted in during SHIFT-IR is

Scan and JTAG Principles

Controller States III * UPDATE-IR • On TCK falling the instruction shifted in during SHIFT-IR is

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TAP Instructions I

*

SCAN_N (0010)

 

Connects the Scan Path Select Register between TDI and TDO.

Selects scan chain for subsequent test operations.

*

EXTEST (0000)

 

Allows for testing of external logic.

During SHIFT-DR scanned-in data is applied immediately to the system.

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INTEST (1100)

Allows for testing of internal logic.

TAP Instructions I * SCAN_N (0010) • Connects the Scan Path Select Register between TDI and
TAP Instructions I * SCAN_N (0010) • Connects the Scan Path Select Register between TDI and

Scan and JTAG Principles

TAP Instructions I * SCAN_N (0010) • Connects the Scan Path Select Register between TDI and

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TAP Instructions II

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IDCODE (1110)

 

Connects device identification register between TDI and TDO.

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BYPASS (1111)

 

Connects a single stage shift register between TDI and TDO.

Allows testing of individual devices to take place.

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CLAMP (0101)

Connects a single stage shift register between TDI and TDO.

Output signals are defined by values previously loaded into the currently selected scan chain.

TAP Instructions II * IDCODE (1110) • Connects device identification register between TDI and TDO. *
TAP Instructions II * IDCODE (1110) • Connects device identification register between TDI and TDO. *

Scan and JTAG Principles

TAP Instructions II * IDCODE (1110) • Connects device identification register between TDI and TDO. *

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TAP Instructions III

*

HIGHZ (0111)

Connects a single stage shift register between TDI and TDO.

All tri-state outputs are inactive, but data supplied to outputs is

All outputs are forced to high impedence state.

*

CLAMPZ (1001) NB. ARM-SPECIFIC

• Connects a single stage shift register between TDI and TDO. •

derived from the scan cells.

*

SAMPLE/PRELOAD (0011)

Selects the boundary scan register as DR, and samples or preloads the chip I/Os.

TAP Instructions III * HIGHZ (0111) • • Connects a single stage shift register between TDI
TAP Instructions III * HIGHZ (0111) • • Connects a single stage shift register between TDI

Scan and JTAG Principles

TAP Instructions III * HIGHZ (0111) • • Connects a single stage shift register between TDI

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ARM Implementation Details

*

ARM7 family cores have *no* boundary scan.

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SAMPLE/PRELOAD instructions must not be used.

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3 Scan chains are available as test data registers.

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JTAG inputs (TDI andTMS) have no internal pullups and must be driven correctly at all times.

ARM Implementation Details * ARM7 family cores have *no* boundary scan. * SAMPLE/PRELOAD instructions must not
ARM Implementation Details * ARM7 family cores have *no* boundary scan. * SAMPLE/PRELOAD instructions must not

Scan and JTAG Principles

ARM Implementation Details * ARM7 family cores have *no* boundary scan. * SAMPLE/PRELOAD instructions must not

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Summary

*

Serial test methods offer a route towards an automated method of providing test coverage.

*

IEEE 1149 extends this serial test architecture to cover system level testing.

*

ARM implements key components of the 1149 standard within its debug-aware cores, but requires external support to completely adhere to the standard.

Summary * Serial test methods offer a route towards an automated method of providing test coverage.
Summary * Serial test methods offer a route towards an automated method of providing test coverage.

Scan and JTAG Principles

Summary * Serial test methods offer a route towards an automated method of providing test coverage.

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