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MOS Transistor
An MOS structure is created by superimposing several
layers of conducting, insulating, and transistor forming
materials to create sandwich like structure shown in fig 1.
A MOS transistor can be modeled as a 3-terminal device
that acts like a voltage controlled resistance. As suggested
by Figure 2 an input voltage applied to one terminal
controls the resistance between the remaining two
terminals.
In digital logic applications, a MOS transistor is operated
so its resistance is always either very high (and the
transistor is off) or very low (and the transistor is on).
Fig. 1
3
MOS Transistor
MOS Transistor
The basic electrical properties of the semiconductor (Si), the
equilibrium concentration of mobile carriers in Si ,always obeys the
Mass Action Law given by,
Fermi Potential
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MOS Transistor
Compared to the bipolar junction transistor (BJT), the MOS
transistor occupies a relatively smaller silicon area, and its
fabrication used to involve fewer processing steps.
There are two types of MOS transistors, n-channel and pchannel; the names refer to the type of semiconductor material
used for the resistance-controlled terminals. The circuit symbol
for an n-channel MOS (NMOS) transistor is shown in Figure 2.
MOS Transistor
The terminals are called gate, source, and drain. The
voltage from gate to source (Vgs) in an NMOS transistor is
normally zero or positive. If Vgs = 0, then the resistance
from drain to source (Rds) is very high, in the order of a
megohm (106 ohms) or more. As we increase Vgs (i.e.,
increase the voltage on the gate), Rds decreases to a very
low value, 10 ohms or less in some devices.
In an n-MOS transistor the majority carriers are electrons.
A positive voltage applied on the gate with respect to the
substrate enhances the number of electrons in the channel
and hence increases the conductivity of the channel.
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Threshold Voltage
Work function difference is
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Threshold Voltage
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Threshold Voltage
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MOSFET Operation
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MOSFET Operation
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MOSFET Operation
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Now assume that the entire channel region between the source and
The drain is inverted,
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Fig (a)
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Eq. -1
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Fig (b)
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But
To simplify the analysis even further, we will use following
Empirical relation between L and VDS
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Body Effect
The threshold voltage is not constant with respect to the VSB .
This is known as substrate bias effect or body effect.
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MOSFET Capacitances
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MOSFET Capacitances
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MOSFET Capacitances
Oxide Related Capacitances:
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MOSFET Capacitances
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MOSFET Capacitances
Cut Off Mode: Cgs = Cgd = 0 and
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MOSFET Capacitances
Linear Mode: Cgb = 0 and
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MOSFET Capacitances
Saturation Mode: Cgd = Cgb = 0 and
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MOSFET Capacitances
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MOSFET Capacitances
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MOSFET Capacitances
Junction Capacitances (Csb and Cdb):
Fig-1
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MOSFET Capacitances
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MOSFET Capacitances
The depletion region thickness (xd):
Eq. 1
Here A is the junction area.
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MOSFET Capacitances
The junction capacitances associated with the depletion region
is defined as
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MOSFET Capacitances
The parameter m in eq-3 is called grading coefficient and
Cj0 is the zero bias junction capacitance per unit area.
Eq-5
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MOSFET Capacitances
For a special case of abrupt p-n junction eq-5 becomes
Eq-6
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MOSFET Capacitances
Assuming that NA (sw) is the sidewall doping density, the
zero bias junction capacitance per unit area Cj0 (sw).
Where 0sw is built in potential. Since all the sidewalls have a same
depth xj , the zero bias junction capacitance per unit length
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MOSFET Capacitances
The voltage equivalence factor Keq (sw)
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MOSFET Capacitances
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MOSFET Capacitances
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MOS Transistor
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N-channel
MOSFET
(NMOS)
uses p-type
substrate
electrons
P-Si
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MOSFET operation
ID
Pinch-off
VG3
VG2
VG1
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' m
Accumulation
of holes
EC
qVG
Ei
EV EFs
E oxide
0
x
Negative voltage
attracts holes to
the Si-oxide interface.
This is called
accumulation condition.
Ei EF should
increases near the
surface of Si.
1 Ei
E oxide const.
q x
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VG < 0
p-type Si
O
E
charge density
small
+
Sheet of
electrons
Sheet of
holes
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positive
Depletion
+
+
EC
Ei
EFs
EV
EFM
M
----
----
negative
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Immobile
acceptors
+
+
EC
+
+
Ei
EFS
-------------
EV
EFM E
Mobile
electrons
FM
x
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Inversion condition
If we continue to increase the positive gate voltage, the bands at
the semiconductor bends more strongly. At sufficiently high
voltage, Ei can be below EF indicating large concentration of
electrons in the conduction band.
We say the material near the surface is inverted. The inverted
layer is not gotten by doping, but by applying E-field. Where did
we get the electrons from?
Energy band
diagrams and
charge density
diagrams
describing MOS
capacitor in n-type
Si
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Example 1
Construct line plots that visually identify the voltage ranges
corresponding to accumulation, depletion and inversion in ideal ntype Si (i.e. p-channel) and p-type Si (i.e. n-channel) MOS devices.
Answer:
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