EE587

SoC Design & Test

Partha Pande
School of EECS
Washington State University
pande@eecs.wsu.edu

Lecture 1

Lecture 1
Design and Technology Trends
Overview

Lecture 1

Recent Trends
1.5GHz Itanium chip (Intel), 410M tx, 374mm2 , 130W@1.3V
1.1 GHz POWER4 (IBM), 170M tx, 115W@1.5V
if these trends continue, power will become unmanageable

150Mhz Sony Graphics Processor, 7.5M tx (logic) + 280M tx

(memory) = 288M tx, 400mm2 10W@1.8V
if trend continues, most designs in the future will have a high percentage of
memory

Single-chip Bluetooth transceiver (Alcatel), 400mm2,

150mW@2.5V
required 30 designers over 2.5 years (75 person-years)
if trend continues, it will be difficult to integrate larger systems on a single
chip in a reasonable time

Lecture 1

Multi-Core Design
Intels 80-core chip
In 65-nm technology with 80 single-precision, floating point
cores delivers performance in excess of a teraflops while
consuming less than 100 w.
A 2D on-die mesh interconnection network operating at 5
GHz provides the high-performance communication fabric to
connect the cores.
Interconnects are the biggest bottleneck
We need to look beyond the metal/dielectric-based planar
architectures
Optical, 3D integration and Wireless are the emerging
alternatives

Lecture 1

Multi-core applications

Nokia Sparrow

Intel LARRABEE

Lecture 1

Three-Dimensional Integrated Circuits

Coming in a big way
Multiple Layers of Active Devices
Driven by
Limited floorplanning choices
Desire to integrate disparate technologies (GaAs, SOI, SiGe,
BiCMOS)
Desire to integrate disparate signals (analog, digital, RF)
Interconnect bottleneck
As small as 20m

2D IC

3D IC
6

Lecture 1
6

Photonic Communication
High bandwidth photonic links for high payload transfers
Limitations on switch architecture
More than 4-port designs are complex

On-chip integration of photonic components

Lecture 1

On-Chip RF/Wireless Interconnects

Replace long distance wires

Use of waveguides out of
package or IC structures like
parallel metal wires
Chang et al. demonstrated
Transmission Line based RF
interconnect for on chip
communication
Not really wireless

Lecture 1

Novel interconnect paradigms for Multicore designs

Three Dimensional
Integration
Wireless/RF
Interconnects

Optical Interconnects

Lower Latency
and Energy
Dissipation
Lecture 1

MOS Transistor Scaling

(1974 to present)

Scaling factor s=0.7 per node (0.5x per 2 nodes)

Metal pitch

Technology Node
set by 1/2 pitch
(interconnect)

Poly width
Gate length
(transistor)

Lecture 1

10

Ideal Technology Scaling (constant field)

Quantity

Before Scaling

After Scaling

Channel Length

L = L * s

Channel Width

W = W * s

Gate Oxide thickness tox

tox = tox * s

Junction depth

xj

xj = xj * s

Power Supply

Vdd

Vdd = Vdd * s

Threshold Voltage

Vth

Vth = Vth * s

Doping Density, p
n+

NA
ND

NA = NA / s
ND = ND / s
Lecture 1

11

Technology Nodes 1999-2019

1999

2001
0.7x

2004

2007

2010

2013

2016

2019

0.7x

180nm 130nm 90nm 65nm 45nm 32nm 22nm 16nm

0.5x
N-1

N+1

Two year cycle between nodes until 2001, then 3 year cycle begins.

Lecture 1

12

MPU Clock Frequency Trend

Intel: Borkar/Parkhurst

1000

100
80386
80486
Pentium
PentiumII
10
Dec-83

Expon.
Dec-86

Dec-89
Lecture 1

Dec-92

Dec-95

Dec-98
13

MPU Clock Frequency Trend

10000

Forward projection
may be too optimistic
P4

1000

100
80386
80486
Pentium
Pentium II
10
Dec-83

Expon.
Dec-86

Intel: Borkar/Parkhurst

Dec-89

Dec-92

Dec-95

Lecture 1

Dec-98

Dec-99

Dec-00

Dec-01 Dec-02

14

MPU Clock Cycle Trend (FO4 Delays)

Intel: Borkar/Parkhurst

100.00

80386
80486
Pentium
PentiumII
Expon.
10.00
Dec-83

Dec-86

Dec-89
Lecture 1

Dec-92

Dec-95

Dec-98
15

Optimal Sizing - FO4 Concept

Delay vs Fanout
6

where is ratio of

5
=0.0

Delay

=0.5

=1.0

=2.0

Parasitic output
Capacitance to gate

capacitance

0
0

Fanout

1X

4X

16X

CIN

Cload

Lecture 1

Use FO4 delay

as optimal delay
16

Clock cycle trend

FO4
delay

1000ps = 25 FO4
Data

L o g ic

Q
N

C lk

40ps

C lk

Clock
(b)

(a)

Lecture 1

17

MPU Trends - Moores Law

Transistors Double
Every Two Years

10,000

1,000

100
100

Transistors
(MT)

10

P6
486

Pentium proc

386
0.1

286
8085

0.01

0.001

Source: Intel

70

4004

2X Growth
in 2 Years!

8086
8080
8008

80

90

Lecture 1

00

10

18

More MPU Trends

~40mm Die in 2010?

100

28

32

36

41

Pentium Pro proc

Die size
(mm)

486

10

Pentium proc

386
8080
8008
4004

8086
8085

286

~7% growth per year

~2X growth in 10 years

1
70

80

90

00

10

Source: Intel
Lecture 1

19

What about power in the future?

Power Projections Too High!
Suns Surface
Rocket Nozzle

10,000

1,000

Nuclear Reactor
HotPentium
Plate

100

processors

Power
(Watts)

286
8086

10

8085
8080

486
386

8008
4004

0.1

Source: Intel

71

74

78

Lecture 1

85

92

00

04

08

20

Problem with Power and Speed

Power knob running out

Speed == Power
10W/cm2 limit for convection cooling, 50W/cm2 limit for forced-air cooling
Large currents, large power surges on wakeup
Die size will not continue to increase unless more memory is used to occupy
the additional area
additional power dissipation coming from subthreshold leakage

Speed knob running out

Historically, 2x clock frequency every process generation
1.4x from device scaling
1.4x from pipelining, hence fewer logic stages (from 40-100 down to around 16 FO4
INV delays)

Clocks cannot be generated with period < 6-8 FO4 INV delays
Around 14-16 FO4 INV delays is limit for clock period

Unrealistic to continue 2x frequency trend!

Lecture 1

21

Low-Power Application: PDA

MM Application

0.18um / 400MHz / 470mW (typical)

MP3
JPEG
Simple Moving Picture

Available Time
6-10Hr

CPG

PWR

PWM RTC

CPU

FICP SSP

Sound

I2C

USB

USB OST

GPIO

MMC

KEY

UART AC97

4 48MHz

I-cache D-cache
32KB 32KB

6.5MTrs.
Max 400MHz

DMA controller

MMC

Peripheral Area

Processor
Area

I2S

MEM
Cnt.

LCD
Cnt.

SDRAM Flash LCD

64MB
Lecture 1

32MB

Data Transfer
Area
100MHz
22

Trends in Low-Power Design Content

Today, SoC designs contain embedded processing engines
such as CPU and DSP, and memory blocks such as SRAM and
embedded DRAM
As we scale technology and keep power constant how does the
amount of logic vs. memory change?
Consider the following assumptions to develop trends for onchip logic/memory percentages
Die size is 100mm2
Clock frequency starts at 150MHz increases by about 40% per
technology node
Average power dissipation in limited to 100mW at 100oC
Initial condition at Year 2001: area percentage 75% logic, 25%
memory
Lecture 1

23

ASIC Logic/Memory Content Trends

Source: Dataquest (2001)

ASIC Core Composition Breakout

60
Percentgae of Die Area
(I/Os Excluded)

50
Random Logic

40

Memory

30

Analog

20

Cores

10
0
1999

2000

Lecture 1

2001

24

Design Trend: Productivity Gap

Year

Technology

Chip Complexity

ASIC Frequency

1997

250 nm

50M Tr.

100MHz

1999

180 nm

150M Tr.

200MHz

2002

130 nm

250M Tr.

400MHz

2004

90 nm

500M Tr.

600MHz

Lecture 1

25

Designing a 50M Transistor IC

Gates Required
Gates/Day (Verified)
Total Eng. Days
Total Eng. Years
Cost/Eng./Year
Total People Cost
Other costs (masks, tools, etc.)

~12.5M
1K (including memory)
12,500
35
$200K
$7M
$8M

Actual Cost is $10-15M to get actual prototypes after fabrication.

Lecture 1

26

Productivity Gap

Deep submicron (DSM) technology allows hundreds of millions of

transistors to be integrated on a single chip

Number of transistors that a designer can design per day (~1000

gates/day) is not going up significantly

New design methodologies are needed to address the

integration/productivity issues

System on a chip Design with reusable IP (Intellectual Property)

new design methodology, IP development
new HW/SW design and verification issues
new test issues

Lecture 1

27

SoC Design Hierarchy

SOC consists of new logic blocks and existing IP
New Logic blocks
Existing IP including memory

Each logic block can be implemented

by newly designed portion and a re-use
portion based on IPs
Newly designed portion
Re-use portion including memory

Lecture 1

28

SoC Platform Design Concept

Pre-Qualified/Verified
Foundation-IP*

Foundation Block + Reference Design

MEM
Hardware IP
SW IP

Application
Space CPU
FPGA

Processor(s), RTOS(es)
and SW architecture

Methodology / Flows:

Programmable IP
*IPcan
canbe
behardware
hardware(digital
(digital
*IP
oranalog)
analog)or
orsoftware.
software.
or
IPcan
canbe
behard,
hard,soft
softor
or
IP
firm(HW),
(HW),source
sourceor
or
firm
object(SW)
(SW)
object

Scaleable
bus, test, power, IO,
clock, timing architectures

System-level performance
evaluation environment
HW/SW Co-synthesis
SoC IC Design Flows
Foundry-Specific
Pre-Qualification

Lecture 1

SoC Verification Flow

System-Level Performance
Evaluation
Rapid Prototype for
End-Customer Evaluation
SoC Derivative Design
Methodologies
29

Purpose of this Course

This course addresses SoC design & test in DSM technologies

The goal is to present an overview of the various issues from
Systems to Silicon to provide a perspective on what is
happening in technology and design.
It is a very broad subject, one that industry is grappling with on a
daily basis one course cannot address all the issue properly
We will begin with the Systems Level and work our way down to
the Circuits Level
The projects, presentations, and assignments will provide indepth analysis of the subjects that are of interest to you

Lecture 1

30

Syllabus
Three broad categories
System on chip design and design for testability
Role of interconnects in contemporary SoC Design
Importance of Power and Low power SoC design
methodology

Lecture 1

31

References

Analysis and Design of Digital Integrated Circuits - In Deep

Submicron Technology, Hodges, Jackson and Saleh, McGrawHill, Third Edition, 2004
Essentials of Electronic Testing for Digital, Memory and MixedSignal VLSI Circuits by M. L. Bushnell and V. D. Agrawal,
Boston: Springer, 2005, ISBN 0-7923-7991-8
Journal Papers, Conference Papers, Course Notes.

Lecture 1

32

Assignments
There will be several homework and reading assignments. In
reading assignments students are expected to read research
papers and submit summaries. The reading list will be available
on the course website. In class, you will be told which papers
you should review.
Each student will have the opportunity to present one paper to
the class. The list of papers will be available in the course
website. Each student should choose one of the listed papers.

Lecture 1

33

Project

One Design Project

List of possible projects will be provided
You are free to choose your own project. In that case
Instructors approval is needed.

Lecture 1

34