Chapter 7 - Sequential Systems

INTRO. TO COMP. ENG.
CHAPTER VII-1
CHAPTER VII
SEQUENTIAL SYSTEMS
CHAPTER VII
SEQUENTIAL SYSTEMS - LATCHES & REGISTERS
Reading Material:
Ch. 7 of Wakerly
Latches and Registers in eBook
R.M. Dansereau; v.1.0
SEQUENTIAL SYST.

CHAPTER VII-2
INTRODUCTION
SEQUENTIAL SYSTEMS
SEQUENTIAL SYSTEMS
-INTRODUCTION
Logistics:
Exam 2 on next Tuesday (March 10)
Will cover the following chapters from the ebook:
Number Systems -- SM, DRC, RC,
Arithmetic addition, subtraction,
Building Blocks combinational circuits,
and Latches and Registers -- sequential circuits
Homework #5 is posted and due Sunday(3/8) at 11:55 pm
Assembly Language
Instruction Set
Memory
Datapath
Controller
Storage
Functional Units
State Machines
Building Blocks
Gates
andStructures/Design
Wire
TaxonomySwitches
of Computing
hierarchy

CHAPTER VII-2
SEQUENTIAL SYST.
SEQUENTIAL SYSTEMS
INTRODUCTION
So
far...
So far we have dealt only
with combinational logic
where the output is formed
from the current input.
SEQUENTIAL SYSTEMS
-INTRODUCTION
Input
Combinational Output
Logic
Sequential systems
Sequential systems extend the idea of combinational logic by including a
system state, or in other words memory, to our system.
This allows our system to perform operations that build on past
operations in a sequential manner (i.e. one after another).
Timing diagrams will be needed to analyze the operation of many
sequential systems.

CHAPTER VII-3
SEQUENTIAL SYSTEMS
SEQUENTIAL SYST.
MEALY & MOORE MACHINES
Mealy machine
Sequential system where
Input
output depends on current

input and state.
Moore machine
Sequential system where
output depends only on
current state.
SEQUENTIAL SYSTEMS
-INTRODUCTION
Sequential System
Combinational
Logic
Output
Memory
(state)
Input
Sequential System
Combinational
Logic
Memory
(state)
Output
Latches and flip-flops are the basic building blocks of most sequential
circuits.

CHAPTER VII-4
SEQUENTIAL SYSTEMS
STORING BITS
STORING A BIT
SEQUENTIAL SYSTEMS
-INTRODUCTION
-MEALY & MOORE
Since there are propagation delays in real components, this time delay can
be used to store information.
For instance, the following buffer has a propagation delay of t p d .
A
F
tpd
Timin
g
Diagra
m
A
F
STORING BITS

CHAPTER VII-5
FEEDBACK LOOPS
SEQUENTIAL SYSTEMS
SEQUENTIAL SYSTEMS
STORING BITS
-STORING A BIT
If we wish to store data for an indefinite period of time, then a feedback

loop can be used to maintain the bit.
0
tpd
Can replace buffer with two inverters!
2 tpd
2 tpd
1
tpd

CHAPTER VII-5
SEQUENTIAL SYSTEMS
STORING BITS
FEEDBACK LOOPS
SEQUENTIAL SYSTEMS
STORING BITS
-STORING A BIT
If we wish to store data for an indefinite period of time, then a feedback

loop can be used to maintain the bit using two inverters
Analog
analysis of
circuit
How do we get the bit we want to store into the feedback loop?

CHAPTER VII-9
SEQUENTIAL SYSTEMS
LATCHES
SR LATCH (NOR GATES)
LATCHES
-CONSTRUCTING A LATCH
-SR LATCH -NAND GATES
-MIXED LOGIC EQUIV.
The SR latch also uses feedback to store a bit.

R (reset)
S (set)
S R Q Q
1 0 1 0
0 0 1 0 (after S = 1, R =
0)
0 1 0 1
0 0 0 1 (after S = 0, R =
1)
1 1 0 0 (invalid)
S R Q Q
0
Q Q
0
1
1
1
0
1
0 1
1 0
0 0
Recall:
A
B
NOR
0 0
0 1
1 0
1 1
1
0
0
0

CHAPTER VII-9
SEQUENTIAL SYSTEMS
LATCHES
SR LATCH (W/ ENABLE)
The SR latch also uses feedback to store a bit.
R (reset)
CLK
S (set)
LATCHES
-MIXED LOGIC EQUIV.
Recall:
A B
NAND
0
0
0
1
1
0
1
1
1
0
0
0
CLK S R Q Q
CLK S R Q Q
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Q
Q
0
1
0
Q
Q
1
0
0
Action
No Change/Hold
No Change/Hold
Reset
Set
(invalid)
0 X X Q Q
1 1 0 1 0
1 0 0 1 0
1 0 1 0 1
1 0 0 0 1
1 1 1 0 0
(after S = 1, R = 0)
(after S = 0, R = 1)
(invalid)

CHAPTER VII-8
SEQUENTIAL SYSTEMS
SR LATCH (NAND GATES)
LATCHES
-D LATCH (WITH TG)
-NAND PRIMITIVES
NAND gates can also be used to create a latch, this time an SR latch.
S R Q Q
1 0 0 1
Q
1 1 0 1 (after S = 1, R =
0)
0 1 1 0
1 1 1 0 (after S = 0, R =
Q
R (reset)
1)
0 0 1 1 (invalid)
Recall:
A B
NAND
0
0
1
0
1
1
1
0
1
Notice that this latch is level-sensitive.
1
1
0
S
(set)
LATCHES

CHAPTER VII-10
SEQUENTIAL SYSTEMS
LATCHES
SR LATCH WITH CONTROL
LATCHES
-MIXED LOGIC EQUIV.
-SR LATCH -NOR GATES
A control line can be added to the SR latch as follows forming an SR latch

S
CLK
This control line makes it possible to decide when the inputs S and R
are allowed to change the state of the latch.

CHAPTER VII-11
SEQUENTIAL SYSTEMS
LATCHES
D LATCH (WITH SR LATCH)
LATCHES
-MIXED LOGIC EQUIV.
-SR LATCH W/ CONTROL
A D latch can be implemented using what is effectively the SR latch with a

control line as follows.
D
CLK
R
Note that as long as CLK = 1 , that the latch will change according to
the value of D .

CHAPTER VII-12
SEQUENTIAL SYSTEMS
LATCHES
TIMING DIAGRAMS
LATCHES
-D LATCH
Timing diagrams allow you to see how a sequential system changes with
time using different inputs.
For instance, a timing diagram for a D latch might look like the
following.
CLK
D
Q
Q
Time

CHAPTER VII-6
STORING BITS
SEQUENTIAL SYSTEMS
LOADING A BIT
SEQUENTIAL SYSTEMS
STORING BITS
-STORING A BIT
-FEEDBACK LOOPS
To store a bit, we need a way of loading an input bit into the structure and
making/breaking the connection in the feedback look.
One way of breaking connections is to use transmission gates.
S1
A
S2
Note: The latch is level-sensitive.
TG
If A changes while S1 = 1, then

Q will change as well.
TG
Q
Q
A gets temporarily stored in the inverters when S 1

0 . Then setting S 1 =
held in the feedback loop.
0 and S 2
= 1 and S 2 =
= 1 , A gets

CHAPTER VII-7
SEQUENTIAL SYSTEMS
LATCHES
D LATCH (WITH TG)
STORING BITS
-STORING A BIT
-FEEDBACK LOOPS
-LOADING A BIT
The previous example is a data latch (D latch) if both S 1 and S 2 are

controlled by a single line C as follows.
Note: The latch is level-sensitive.
C
(Enable)
TG
D
TG
If D changes while C = 1,
then Q will change as well.
Q
Q
The control line C might be derived from the clock signal, or a signal
from the controller/sequencer in the microprocessor.

CHAPTER VII-13
SEQUENTIAL SYSTEMS
LATCHES
TRANSPARENCY (1)
LATCHES
-D LATCH
-TIMING DIAGRAMS
Latches like the D latch are termed transparent or level-sensitive.

This is because, when enabled, the output follows the input.
Enable
IN
Transparen
t Latch
Enable
OUT
Q
Q
Note:
Transparen
t
LATCHES

CHAPTER VII-14
TRANSPARENCY (2)
SEQUENTIAL SYSTEMS
LATCHES
-D LATCH
-TIMING DIAGRAMS
-TRANSPARENCY
The following behaviour is observed for Enable = 0 and Enable = 1.
IN
When Enable = 0,
input disconnected and
stored bit outputed.
Transparen
t Latch
OUT
When Enable = 1,
latch acts like wire.
Enable
Stored
bit
IN
OUT
0
IN
OUT
1

CHAPTER VII-15
SEQUENTIAL SYSTEMS
LATCH EXAMPLE
PROBLEMS W/ TRANSPARENCY
LATCHES
-D LATCH
-TIMING DIAGRAMS
-TRANSPARENCY
A problem with latches is that they are level-sensitive.

A momentary change of input changes the value passed out of the latch.
This is a problem if the input of a latch depends on the output of the same
latch.
Example: Design a system that flips a stored bit whenever Enable goes
high.
An inexperienced engineer might design the following.

How will this design behave?
Transparen
t Latch
Enable
Will the bit flip once when the

Enable signal goes high?
Answer: The output will
follow the input, which
happens to keep
changing.

CHAPTER VII-16
SEQUENTIAL SYSTEMS
LATCH EXAMPLE
PROBLEMS W/ TRANSPARENCY
LATCHES
LATCH EXAMPLE
-PROB W/TRANSPARENCY
Lets analyze the timing behaviour of this poor design.

Notice that instead of the desired
bit flip when Enable=1, that the
input oscillates.
A
B
Enable
because the output depends

directly on the input since A and
B appear to be connected by a
wire.
Enable
A
B
This is

CHAPTER VII-17
SEQUENTIAL SYSTEMS
LATCH EXAMPLE
ELIMINATING TRANSPARENCY
LATCHES
LATCH EXAMPLE
The problem with transparent, level-sensitive latches can be fixed by

splitting the input and output so that they are independent.
New solution:
Consider the following improved design that flips a
stored bit whenever Enable goes high. This design now uses a master
and a slave transparent latches to separate the input from the output.
Master
Transparen
t Latch
Transparen
t Latch
Enable
Enable
Slave

CHAPTER VII-18
LATCH EXAMPLE
SEQUENTIAL SYSTEMS
LATCHES
LATCH EXAMPLE
-ELIMIN. TRANSPARENCY
TIMING DIAGRAM
Lets analyze the timing behaviour of this improved design.

Transparen
t Latch
Enable
Enable
Enable
A
B
C
Transparen
t Latch
B
Enable
LATCH EXAMPLE

CHAPTER VII-19
LATCH BEHAVIOUR
SEQUENTIAL SYSTEMS
LATCH EXAMPLE
-TIMING DIAGRAM
The behaviour of the master and the slave transparent latches can be
thought of as follows.
Enable = 1
bit
A
Enable = 0
bit
A

CHAPTER VII-20
SEQUENTIAL SYSTEMS
FLIP-FLOPS
LATCH EXAMPLE
-TIMING DIAGRAM
-LATCH BEHAVIOUR
SINGLE BIT STORAGE
A flip-flop is a single bit storage unit with two stages (master/slave):

First stage, or master, to accept input (flip)
Second stage, or slave, to give output as received by the first stage
(flop)
IN
Transparen
t Latch
Transparen
t Latch
Enable
Enable
OUT
IN
OUT
Enable
A number of different types of flip-flops exist such as the SR, SR , D,

and JK flip-flops.
types.
You may wish to review Chapter 4 regarding these

CHAPTER VII-21
SEQUENTIAL SYSTEMS
FLIP-FLOPS
EDGE TRIGGERED
LATCH EXAMPLE
FLIP-FLOPS
-SINGLE BIT STORAGE
A common and useful type of flip-flop are edge triggered flip-flops.

Positive edge triggered flip-flops
IN
Transparen
t Latch
Transparen
t Latch
Enable
Enable
OUT
Negative edge triggered flip-flops

IN
Transparen
t Latch
Transparen
t Latch
Enable
Enable
OUT

CHAPTER VII-22
SEQUENTIAL SYSTEMS
FLIP-FLOPS
NEGATIVE EDGE TRIGGERED
LATCH EXAMPLE
FLIP-FLOPS
-SINGLE BIT STORAGE
-EDGE TRIGGERED
The output C, which is also the bit stored, appears to change on the
negative edge of the Enable transitions.
IN
A
Enable
Enable
A
B
C
Transparen
t Latch
Enable
Transparen
t Latch
B
Enable
OUT
C

CHAPTER VII-23
SEQUENTIAL SYSTEMS
FLIP-FLOPS
POSITIVE EDGE TRIGGERED
FLIP-FLOPS
-SINGLE BIT STORAGE
-EDGE TRIGGERED
-NEG. EDGE TRIGGERED
The output C, which is also the bit stored, appears to change on the
positive edge of the Enable transitions.
IN
A
Enable
Enable
A
B
C
Transparen
t Latch
Enable
Transparen
t Latch
B
Enable
OUT
C

CHAPTER VII-24
SEQUENTIAL SYSTEMS
FLIP-FLOPS
NON-IDEAL W/ DUAL-PHASE
The previous timing diagrams are in an ideal case.
FLIP-FLOPS
-EDGE TRIGGERED
-POS. EDGE TRIGGERED
In reality, an
implementation with delays might have the following timing diagram.

1
2
A
B
Propagation
delays shift
the outputs and
skew transitions
Notice that Enable /Enable are replaced with 1 /2 , which are nonoverlapping phases (normally generated from a dual-phase clock).

CHAPTER VII-25
SEQUENTIAL SYSTEMS
FLIP-FLOPS
DUAL-PHASE ENABLE
FLIP-FLOPS
-NON-IDEAL W/DUAL-
Why use non-overlapping, dual-phase signals for the latch enable?

What happens if the latch enable input flip simultaneously?
How about if propagation delays cause one latch to change enable
state slightly before the other?
The goal is to ensure that the master latch has latched the input
before the slave latch tries takes this bit from the master.
IN
Transparen
t Latch
Transparen
t Latch
OUT
IN
1-bit
flip-flop
OUT
1 2
If the master has not latched, the slave sees the input transparently!!!
A non-overlapping, dual-phase enable solves this problem.

CHAPTER VII-26
SEQUENTIAL SYSTEMS
REGISTERS
REGISTERS FROM FLIP-FLOPS
Assembly Language
Instruction Set
Memory
Datapath
Controller
Storage
Functional
Units
State
Machines
Building Blocks
Gates
Switches and Wire
FLIP-FLOPS
-NON-IDEAL W/DUAL-
-DUAL-PHASE ENABLE

CHAPTER VII-26
SEQUENTIAL SYSTEMS
REGISTERS FROM FLIP-FLOPS
In essence, a flip-flop is a 1bit register.
REGISTERS
A0
1-bit
flip-flop
D0
A1
1 2
1-bit
flip-flop
D1
An n-bit register can be

formed by grouping n flipflops together.
FLIP-FLOPS
-NON-IDEAL W/DUAL-
-DUAL-PHASE ENABLE
1 2
An 1
1-bit
flip-flop
1 2
1 2
Dn 1

CHAPTER VII-27
SEQUENTIAL SYSTEMS
REGISTERS
READ/WRITE CONTROL (1)
FLIP-FLOPS
REGISTERS
-REGISTERS F/FLIP-FLOPS
When a clock is used, such as the non-overlapping, dual-phase clock 1

and 2 , we want control over when a new value is written into a register
(instead of writing a new value every clock cycle).
A read/write control is therefore required.
One poor design might be as follows for a 1-bit register.
IN
Read/Write
Transparen
t Latch
Transparen
t Latch
What is the problem with this design?

OUT

CHAPTER VII-28
SEQUENTIAL SYSTEMS
REGISTERS
FLIP-FLOPS
REGISTERS
-READ/WRITE CONTROL
A better design might be as follows
IN
Transparen
t Latch
Transparen
t Latch
OUT
Read/Write
When Read/Write = 0, the output is feed back into the master latch.
When Read/Write = 1, the input is feed into the master latch.

CHAPTER VII-29
SEQUENTIAL SYSTEMS
REGISTERS
FLIP-FLOPS
REGISTERS
-READ/WRITE CONTROL
A different design approach might be as follows

IN
Transparen
t Latch
Transparen
t Latch
OUT
Read/Write
What problems might exist with this design?
One issue might be that both latch enables are 0 when R/W
= 0.

Chapter 7 - Sequential Systems

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INTRO. TO COMP. ENG.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

MEALY & MOORE MACHINES

output depends on current

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

If we wish to store data for an indefinite period of time, then a feedback

Can replace buffer with two inverters!

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

If we wish to store data for an indefinite period of time, then a feedback

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

SR LATCH (NOR GATES)

The SR latch also uses feedback to store a bit.

INTRO. TO COMP. ENG.

SR LATCH (W/ ENABLE)

The SR latch also uses feedback to store a bit.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

SR LATCH (NAND GATES)

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

SR LATCH WITH CONTROL

A control line can be added to the SR latch as follows forming an SR latch

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

A D latch can be implemented using what is effectively the SR latch with a

INTRO. TO COMP. ENG.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

Note: The latch is level-sensitive.

If A changes while S1 = 1, then

A gets temporarily stored in the inverters when S 1

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

D LATCH (WITH TG)

The previous example is a data latch (D latch) if both S 1 and S 2 are

INTRO. TO COMP. ENG.

Latches like the D latch are termed transparent or level-sensitive.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

The following behaviour is observed for Enable = 0 and Enable = 1.

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

A problem with latches is that they are level-sensitive.

An inexperienced engineer might design the following.

R.M. Dansereau; v.1.0

Will the bit flip once when the

INTRO. TO COMP. ENG.

Lets analyze the timing behaviour of this poor design.

because the output depends

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.

The problem with transparent, level-sensitive latches can be fixed by

Consider the following improved design that flips a