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SILICON PROCESSING FABRICATION YIELD

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CHIP DESIGN

BY
SRITEJA TARIGOPULA
SUBMITTED TO
DR. ROMAN STEMPROK

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Overview of Silicon Processing

An integrated circuit (IC) consists of several patterned

layers of materials to form FETs and interconnects

In a modern process :

Minimum feature size < 0.12m

Individual chips with more than 100 million FETs

The techniques needed to fabricate chips of this

sophistication have been developed over several decades at
tremendous cost

CHIP DESIGN

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Silicon Processing - Wafers

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CHIP DESIGN

Si ICs are created on large

circular sheets of Si called
wafers
100-300mm in diameter
~ 0.7 mm thick

Si IC is ~ 1 cm on a side

Many ICs on a single wafer

Location of an IC on a wafer is
called a die site
A flat on the wafer is used as a
reference plane to form a grid
for die placement
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Silicon Processing - Wafers

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The manufacturing capacity of a chip factory is measured

by the number of wafer starts per week
The number of wafer starts indicates how many fresh
wafers are introduced into the fabrication sequence
Wafers are processed in groups, and it typically takes
several weeks for a lot to pass through the entire
processing line

CHIP DESIGN

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Silicon Processing Fabrication Yield

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Not every die site on the Si wafer produces a functional

circuit
Due to many factors inherent in the complexity of the Si processing

To quantify problem, chip manufacturers use the concept of

fabrication yield Y ;
Y = [NG / NT] x 100%

NG = number of good functional sites

NT = total number of sites on wafer

High yield values are critical for IC economic stability

CHIP DESIGN

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Silicon Processing Fabrication Yield

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Yield analysis is based on predicting the yield Y of a

particular IC process
very specialised aspect of VLSI manufacturing
requires thorough understanding of all aspects of Si processing

Yield analysts attempt to optimise Y for a given IC design

work closely with groups on manufacturing line

also work with specialist wafer analysis groups

CHIP DESIGN

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Silicon Processing Effect of die area on yield

A variable that is critically important to increasing the

yield is the area of the die Adie

The total die sites NT on a wafer of diameter d is found as :

NT = (d - de)2 / 4Adie

de = wasted edge distance from placing rectangular die onto round

wafer

Empirical analysis shows that large area die are plagued by

smaller yields

CHIP DESIGN

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Silicon Processing effect of die area on yield

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Defects on the wafer can result in circuit failure and

influence Y
The average number of defects per cm2 is denoted by the
parameter D and quantifies the wafer perfection
for modern IC production D is typically ~ 1 cm-2

For isolated defects :

Y = exp[-(AdieD)]

For clustered defects :

Y = [1 - (AdieD)/c]c

c = empirical parameter that characterises cluster structure

CHIP DESIGN

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Silicon Processing Economic Factors

For economic survival, a Si chip manufacturing plant must be

profitable : profit-per-chip = Csell - Cchip is not easy to estimate

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Cchip = chip production

costs
Cchip includes

Materials
personnel salaries
(design, manufacture,
test etc)
overheads (electricity,
water, taxes etc)
initial plant commission
~ $1-3 billion !!

CHIP DESIGN

Csell = chip selling price

all direct and indirect costs
fraction of plant debt

Csell must however be at level that

customers will pay
high chip demand Csell

whatever market will bear

low chip demand Csell

Withdraw product?

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Silicon Processing Economic Factors

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Notice also that Csell tends to decrease with time !

Hottest new microprocessors eventually become basement bargains
no problem to IC manufacturer provided initial engineering costs
are recouped
original IC design can be very expensive

A helpful factor in IC manufacturing profitability is that as

time progresses :
Cchip Cmaterials

for CMOS Si is very cheap compared to alternatives such as III-Vs

keeping product lines operative for many years therefore improves
overall profitability

CHIP DESIGN

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Refrences

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Introduction to VLSI Circuits and Systems, by John

P.Uyemura
D.Morgan and K.Board, An Introduction to
Semiconductor Microtechnology, J.Wiley & Sons, 1988
http://www.personal.dundee.ac.uk/~dmgoldie/teaching/eg40
13/lectures/1
http://www.stanford.edu/class/ee271/stick_to_layout/stick_
to_layout.html

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Thank you

CHIP DESIGN

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