ADC-BASED EMBEDDED RT

SIMULATOR OF A POWER
CONVERTER IMPLEMENTED
IN AN FPGA
PRESENTED BY

SANJAY KUMAR DHRITLAHARE (15EC65R15)

VIPES, E&ECE Department
IIT KHARAGPUR

OVERVIEW
Introduction to Basic Terms.

Previous approaches & limitations.

Brief intro to proposed approach.
Design constraints for FPGA based
Simulator.
Design Guidelines
Design of ADC-based Embedded RT
Simulator.
Conclusion
References

INTRODUCTION
BASIC TERMINOLOGIES
Associated Discrete Circuit (ADC)

Embedded Real Time (RT) Simulator

Power Converters
FPGA stands for Filed-Programmable Gate
Array

INTRODUCTION

(cont.)

Nowadays, RT digital simulation can be seen as

advanced research field in Power Electronics

Applications.
Most RT simulators are applied in context of
hardware-in-loop (HIL) testing of digital
controllers.
Main issue of interest is to develop RT
simulators able to accurately reproduce the
system dynamics and transients.
4
True for simulating Power Converter.

EXSISTING METHODS
& LIMITATIONS
Average Model Solver (Lack of accuracy).

State-Space Solver.
Only ADC based (high simulation steps)
Only FPGA based RT simulators (very costly)
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PROPOSED APPROACH
Important Information
Simulator is implemented using ADC-based Embedded
RT simulators on low cost FPGA.
Embedded RT simulator :- Intellectual property (IP)
module
IP and controllers both implemented and run on same
FPGA device.
Proved by applying it to a Fault-tolerant grid-connected
3-phase 2-level Voltage-Source Rectifier (VSR).
Thus ADC-based embedded RT simulator is associated
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with one of 3-phase RL filter to find Grid currents

DESIGN CONSTRAINTS FOR

SIMULATOR

Timing Constraints
a.
b.
c.
d.
e.
f.

Choice of appropriate Simulation Time Step (T s).

Ts < 5% to 10% of the smallest time constant of the controlled
system
Ts long enough to process all model equations.
Ts Short enough to accurately represent the system.
RT simulator must be carefully synchronized with the system
controller
Ts at least 100 times less than the smallest switching period to
avoid inter-time-step simulation errors.

Modularity Constraints
a.
b.

To make the design manageable and well structured.

Selection of IP-Library.

DESIGN CONSTRAINTS FOR

SIMULATOR (cont.)

Fig-1. IP-Library for

FPGA-based
embedded
RT
simulators

DESIGN CONSTRAINTS FOR

SIMULATOR (cont.)
Algorithm Constraints
a. Complexity.
b. Data Conditioning.

FPGA Implementation Constraints

a. Parallelism of algorithm.
b. FPGA Integrates
Memory blocks
Hardwired DSP units (e.g., Xilinx DSP48E1)
Hardwire processing systems (e.g., Zynq FPGA dual-core
Cortex-A9 ARM processor)
c. Resource management
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DESIGN GUIDELINES FOR FPGABASED EMBEDDED RT SIMULATOR

4 Major Steps:-

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Preliminary System
Specification.
Algorithm Development.
FPGA Implementation.
Experimentations

DESIGN GUIDELINES FOR FPGABASED EMBEDDED RT SIMULATOR

(cont.)

Fig-2.
Design
guidelines for FPGAbased embedded RT
simulators
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DESIGN OF ADC-BASED
EMBEDDED RT SIMULATOR

Simulated for Grid connected 3-Phase 2-level VSR.

Simulator IP is associated with one of the 3-phase
RL-filter.
Applied in context of a fault tolerant control the
VSR.
These IPs estimate the grid currents (igi (i=a,b,c) ).
When fault on the grid current sensors, the
measurements are then replaced by their
estimates.
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
1. Preliminary System Specification:

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The power stage is composed of

i) 3-phase voltage sources from the grid (230 V

and 50 Hz)
ii) An autotransformer
iii)A three-phase RL-filter (R=0.8, L=20mH)
iv) A 20-KVA 3-phase 2-level VSR with insulatedgate bipolar transistor (IGBT)/diode switches.
v) A capacitor for the DC link (1100 F/800 V)
vi)A resistive load (100/2.5 A)
vii) Contactor to connect and disconnect the
load

Fig-3. Power

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

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The used device is the Xilinx Zynq FPGA SoC ( XC7Z020

ZedBoard ) consists of followings:
1. Integrated dual-core CortexA9 ARM processor
2. 53,200 lookup tables (LUTs)
3. 1,06,400 flip-flops
4. 560KB RAM blocks
5. 220 DSP48E1
6. Analog peripherals
7. Up to 200 high-speed I/O
blocks.
Fig-4. Xilinx Zynq FPGA SoC (XC7Z020
ZedBoard)

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

FPGA Modules:-

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1. Analog-to-digital
conversion module based
on the integrated XADC.
2. DC-link voltage and grid
current regulator.
3. ADC-based embedded RT
simulator module of the
VSR.
4. Embedded RT simulator
of the 3-phase RL-filter

Fig-5. Structure of the developed control

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

a) XADC conversion unit: Analog-to-digital conversion is

achieved using the on-chip
12-bit 1-MSPS ADC.

dual

To ensure conversion of all signals

(, and ), an off-chip analog mux
has been used.

Experimentally
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measured
conversion time = 1.18s.

Fig-6. Synoptic of
XADC conversion unit.

the

DESIGN OF ADC-BASED
EMBEDDED RT SIMULATOR
(cont.)
Sampling period of XDAC is
set to 2s. (considering
settling time of MUX)
Used h/w resources are,
39 LUTs (0.07%)
197 FFs (0.18%)

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Fig-7.
Digital

Analog-toConversion

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
b) DC-link Voltage and Grid Current
Regulator: Chosen control strategy is the Direct Sliding-mode Power

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Control (DSMPC)
Main objective is to keep the DC-link voltage Vdc = Vdc
(Reference voltage) with controlled P.F.
Sampling period of PI regulator is set to 50s.
Used base values are 563V for v/gs and 4A for currents.
For data quantification, fixed-point format is set to
20Q12 (20 total bit no., 12bits in fractional part)
Obtained Latency = 42, Computational time = 420ns
(100MHz system clock).

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
H/w resource used by
controller
7 DSP48E1 units (3.18%) for multiplications
1336 LUTs (2.51%)
1034 FFs (0.97%)

Fig-8. Architecture of the DSMPC controller

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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

20

Table-1. Timing/area performances of DSMPC Controller

modules

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
Embedded RT Simulator of the 3-Phase RL-filter:-

Computes the grid currents from the measured grid

voltages and the line voltages processed by VSR
simulator.
corresponding discrete-time equations are obtained
after a backward Euler approximation and are
expressed as follows:

21

where .R+L) and

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

22

(b
(a
) equivalent ADC-based circuit.
Fig-9.
(a)
Power
converter
topology.
(b)
One-leg
)

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
Simulator is synchronized with the VSR one and has the

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same simulation time step, i.e., = 500ns.

Base values for normalization are same those of
controller (563 V and 4 A).
The chosen fixed-point format is 32Q28 (32 total bit
number and 28 bits in the fractional part)
4 bits are attributed to the integer part to avoid any
overflow.
FPGA architecture is factorized ( methodology) to
optimize the use of multipliers.

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
Only one 32-bit multiplier is
deployed that corresponds to
four DSP48E1 units (each one
integrates
a
2518bit
multiplier).
Used hardware resources are
i. 2 LUTs (0.003%).
ii. 15 FFs (0.014%).
Total Latency = 15, and the
Execution Time = 150ns (with
a 100MHz system clock).
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Fig-10. FPGA-based architecture of the 3phase RL-filter.

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

2. Algorithm Development:

a) Model Selection :Adopted

modeling
approach
allows
representing a switch as an RLC circuit.
Allows a more accurate modelling of
switching dynamics.
An ADC equivalent model represents a
power switch by
i. a small inductance when switch is ON.
ii. a small capacitance when it is OFF.
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
To solve the problem of overshoots and
oscillations, a resistance is placed in
series with the , acting as a damping
element.
Consider shown circuit, During ON
state obtained conductance is given
as,

During OFF state conductance is given

as
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
The relations between voltages and currents of the
whole power converter is given as a matrix equation
where, H is the conductance matrix, Vector x[k]
gathers the node voltages and line voltages and the dc
current Vector b[k] is built from each voltage node of
and and dc voltage .
The system solution is computed at each simulation
time step by solving matrix equation:
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
Extended Matrix Equation

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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
To optimize the complexity and avoid online matrix
inversion, relationship between , , , and that makes
the conductance matrix constant independent of
switch state.
This relation is then

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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
b) Modular Partitioning: Modules are defined for ADC-based model and
that are located in levels 2 and 3 of the IPLibrary.
Each module is subdivided into submodules
from the lower levels.
Processing of the states (ON/OFF) of switches is
first achieved depending on the switching
signals and the switch voltages & currents.
30

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

31

Fig-11. Synoptic of the ADC-based

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
c) Digital Realization: To satisfy the timing constraint,

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of the embedded RT

simulator has been set to 500 ns.

the maximum switching frequency of the used power
converter is equal to 20 kHz.
Thus, is therefore 100 times less than the corresponding
minimum switching period.
Same base values for normalization as those of the
controller are used here (563 V and 4 A).
Fixed-point format has been set to 32Q28 (32 total bit
number and 28 bits in the fractional part)

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

c)
Algorithm
Validation: The

discrete-time and
fixed
point
offline
simulations have been
made with the help of
MATLAB/Simulink tools.
The = 7.5 , = 160H,
and = 1.6nF have been
manually tuned and set .
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Fig-12. Offline simulation results during

switches commutation (h: 50s/div; v: 100
V/div, 1 A/div for IGBT, 0.5 A/div for diode).

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
It is shown that, when injecting these estimated grid currents
to the controller, the load disturbance is correctly compensated
and Vdc remains equal to its reference (set here to 200 V).

unit

power factor
operation is obtained
since the grid current
and voltage remain
in phase.

34

Fig-13. Closed-loop offline simulation results

during load connection (h: 20ms/div; v: 50

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
3. FPGA Implementation:
a) FPGA Architectural Design:Implementing
the
ADC-based
embedded RT simulator IP fully in
hardware and then designing a fully
dedicated architecture is only option.
This fully hardware approach enables
also the portability of the simulator IP.
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

Fig-14.
Designed
FPGA
architecture of the ith element
of vector x[k].

36

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
b) Time/Area Evaluation:-

Fig-15. Timing diagram

37

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
Regarding the 3-phase VSR embedded RT simulator,
the obtained Latency = 28.
Gives a computation time = 280ns (with a 100-MHz
system clock).
Resources Used
i. 180 DSP48E1 units (81.81%)
ii. 3982 LUTs (7.5%).
iii. 6410 FFs (6.02%).
.IP uses 44, 32-bit multipliers to execute 88
multiplications.
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
Finally, the whole architecture, including the controller,
the XADC conversion unit, the 3-phase RL-filter, and VSR
embedded RT simulators, uses 19.68% of the available
13,300 slices
i. 84.54% of the available 220 DSP48E1 units.
ii. 11% of LUTs
iii. 9% of flip-flops
.IP uses 44, 32-bit multipliers to execute 88
multiplications.
39

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
4. Experimentations:
a) HIL Tests: To ensure a first realistic validation of the

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developed control system, an HIL validation

test has been made.
For this, an FPGA-based RT emulator of the
power system under control has been
added to the design.
To debug and to view the internal signals
running in FPGA, the ChipScope analyser
has been used.

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

Fig-16. Closed-loop RT HIL results

during (a) load connection and
(b) at steady state (h: 50ms/div; v: 50
V/div, 2.5 A/div).
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DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)
b) Experimental Validation:Step

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1:
The resistive load (in the dc side) is
disconnected.
All the switching signals applied to
the power converter are set to zero.
The
magnitude of the dc-link voltage was set equal to
190 V by acting on the autotransformer ratio.
Step 2: The computed switching signals are now applied
to the power converter in order to impose the Vdc
voltage equal to its reference (200 V here).
Up to
this step, the measured grid currents were used by
the controller.

DESIGN OF ADC-BASED EMBEDDED

RT SIMULATOR (cont.)

43

Step 3: The resistive load is connected to the dc

link.
Step 4: The estimated grid currents processed are
now used by
the controller instead of
measured ones.
Switching between
measured and estimated currents is done by
a simple switch that is used to model current
sensor fault occurrence.
Step 5: The resistive load is alternatively connected
and disconnected (during fault).

EXPERIMENTAL SETUP

(a
)
44

Fig-17. (a) & (b) Experimental setup

(b
)

RESULTS

45

Fig-18. Measured Vdc and measured and estimated iga during diode VSR
operation mode (h: 50ms/div; v: 50 V/div, 2.5 A/div)

RESULTS (cont.)

46

Fig-19. Measured Vdc and iga before and after current sensor
fault
(h: 20ms/div; v: 50 V/div, 2.5 A/div).

RESULTS (cont.)

47

Fig-20. Measured Vdc and measured and estimated igi(i=a,b,c)

when
the load is disconnected (h: 50ms/div; v: 50 V/div, 2.5 A/div).

RESULTS (cont.)

Fig-21.
Experimental
results during switches
commutation
(h: 50s/div; v: 100 V/div,
1 A/div for IGBT, 0.5 A/div
for diode)

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CONCLUSION
The

Proposed simulator when implemented with the

controller, they can be beneficial form any tasks such
as estimations, observations, diagnostic, health
monitoring, and online identifications.
The Graphs shows that the results are almost same
as estimated. This shows accuracy of the approach
used.
All these IPs were implemented in a low-cost Xilinx
Zynq FPGA SoC device.
Further improvements are intended such as including
the dead time and implementing additional tasks like
online identification algorithms to cope with
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REFERENCES
[1] Mohamed Dagbagi, Asma Hemdani, Lahoucine Idkhajine, Mohamed Wissem Naouar, Ilhem
Slama-Belkhodja. ADC-Based Embedded Real-Time Simulator of a Power Converter
Implemented in a Low-Cost FPGA: Application to a Fault-Tolerant Control of a GridConnected Voltage-Source Rectifier, in IEEE Trans. Ind. Electron., vol. 63, no. 2, February
2016
[2] C. Dufour, T. Ould Bachir, L.-A. Grgoire, and J. Blanger, Realtime simulation of power
electronic systems and devices, in Dynamics and Control of Switched Electronic Systems
SE-15 F. Vasca and L. Iannelli, Eds. London, U.K.: Springer-Verlag, 2012, pp. 451487.
[3] M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, FPGA-based fast detection with
reduced sensor count for a fault-tolerant three-phase converter, IEEE Trans. Ind. Informat.,
vol. 9, no. 3, pp. 13431350, Aug. 2013.
[4] O. Lucaet al., Real-time FPGA-based hardware-in-the-loop simulation test bench applied to
multiple-output power converters,IEEE Trans. Ind. Appl., vol. 47, no. 2, pp. 853860,
Mar./Apr. 2011.
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