SIDDHI VINAYAK COLLEGE OF

SCIENCE & HIGHER EDUCATION

A
SEMINAR
On
VLSI

Subjected By:

Submitted To:

Mr. Vikas

Bhawna Kalra

Tiwari
4th year (ECE)

H.O.D(ECE)

TOPICS

Introduction of VLSI
Advantage of VLSI
Design Flow of VLSI
Module
HDL Languages
Verilog Language
Three Types of Modelling

Future Scope In VLSI

Introduction of VLSI
VLSI Stands for very large scale integration
Its all about integrated circuit design usually we
call it is as chip design.
In VLSI, hundred of thousand transistors or logic
device fabricated in a single chip.

Advantages of VLSI

smaller size
lower cost
low power
higher reliability
more functionality

Design Flow of VLSI

Design flow:

Requirement

VHDL
Verilo
g
Optimizati
on
Net list
generatio
n

Design
HDL & linding test

Front end
designing

Logic synthesis
Circuits design
Physical design
Engineering samples

Bu
g

Verification

Testing
Production

Back end
designing

Validation

HDL Languages
There are two hardware description
languages used for designing VLSI
circuits.
VHDL
VERILOG
So here we deals with the study of
verilog

Verilog Language
Verilog was firstly developed in 1984
VERILOG is case sensitive language.
Originally a modeling language
Virtually every chip (FPGA, ASIC, etc.)
is designed in part using this language.

Two Main Data Types

Nets represent connections between things
Do not hold their value
Cannot be assigned in an initial or always block

Regs represent data storage

Behave exactly like memory in a computer
Hold their value until explicitly assigned in an
initial or always block
Can be used to model latches, flip-flops, etc.

Types of Modeling
1. Structural Modeling
2. Data flow Modeling
3. Behavioral Modeling

Four Valued Data

Verilogs nets and registers hold four-valued data
0, 1
Obvious

Z
Output of an undriven tri-state driver
Models case where nothing is setting a wires value

X
Models when the simulator cant decide the value
Initial state of registers
Output of a gate with Z inputs

Module
Begins with keyword module.
FIVE COMPONENTS within module are
1) variable declaration
2) dataflow statements
3) instantiation of lower modules
4) behavorial blocks
5) tasks or functions
All components except module , module
name and endmodule are optional and
can mixed and matched as per design
needs.

Structural modeling
Low level of Abstraction.
Also known as Gate level modeling.
Circuit is described in terms of gates.
Most logic simulators on netlists.
Not most convenient way to express test
benches.

Example of Gate Level

Mux(4:1)

Gate Dig. Of 4:1 Mux

Verilog Code for 4:1 mux

Data flow modeling

Dataflow modelling provides a very powerful
way to implement design.
For complex designs, the number of gate is
very Large.
It allows circuit to be designed in terms of the
dataflow between registers.
With gate densities increasing on chip
increases rapidly.

Example 4:1 mux

module mux_4_1 (i0, i1, i2, i3, s1, s0, out);
input i0;
input i1;
input i2;
input i3;
input s1;
input s0;
output out;
assign out = (~s1 & ~s0 & i0)|
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3) ;
endmodule

Behavioral modeling
Functionality is described in an algorithmic
manner.
High level of abstraction.
The designer describes the behavior of the
circuit.
There are two structured procedure
statements in behavioral modeling
Always & Initial

Case Statement

The keywords case, end case, default are used in case

statement.
Example
4:1 mux using case

Future Scope In VLSI

Front End designing

Back End Designing

Validation Part

Verification Team

THANK

YOU