Synopsys Tools for Verilog Simulation

VCS - Verilog simulator tool

-Get manual by using vcs -doc

-Run GUI by using vcs -RI

%vcsfoo.v

Compiles the Verilog into an executable binary

Simulation executable (simv)

%simv

Simulates the Verilog by running the executable

You may use the GUI to control simulation and view results

Setup to Run Synopsys Tools

% module load synopsys/vcs

- sets up key environment variables
% module load acroread
- needed to run see manual (vcs -doc)

vcs GUI/manual (-RI, -doc) is an X application so:

Run an Xclient on your local machine
Set remote DISPLAY variable to local display
Give CS machine permission to control your DISPLAY
Ask CS support about how to do these things

Running a Basic Simulation

%vcs sig_ctrl.v

Only $display/$monitor statements will appear

%simv

There are many compiler and execution options (see vcs

manual)

%vcs -I sig_ctrl.v

-I option compiles for interactive (debugging) mode

%simv

Simulation will occur and you will get a command line

interface (CLI) prompt

-RI option compiles for interactive mode and starts GUI

%vcs -RI sig_ctrl.v

GUI allows you to run simulation and debug

Verilog Basics, Modules

moduleT_FF(q,clock,reset);
.
.
.
.
endmodule

Similar to a class, can be instantiated many times

I/O ports declared at the top
Typically represents a physical component
Can be structurally connected to other components
Cannot be invoked like a function

Levels of Abstraction

Behavioral
Procedural code, similar to C programming
Little structural detail (except module interconnect)
Dataflow
Specifies transfer of data between registers
Some structural information is available (RTL)
Sometimes similar to behavior
Structural (gate,switch)
Interconnection of simple components
Purely structural

Instances

moduleTFF(q,clk,reset);
outputq;
inputclk,reset;
wired;
DFFdff0(q,d,clk,reset);
notn1(d,q);
endmodule

moduleripple_carry_counter(q,clk,reset);
output[3:0]q;
inputclk,reset;
//4instancesofthemoduleTFFarecreated.
TFFtff0(q[0],clk,reset);
TFFtff1(q[1],q[0],reset);
TFFtff2(q[2],q[1],reset);
TFFtff3(q[3],q[2],reset);
endmodule

TFF is instantated within ripple_carry_counter

DFF and not are instantiated within TFF
Structural interconnect is established through instantiation

Testbench (Stimulus Block)

modulestimulus;
regclk;
regreset;
wire[3:0]q;
//instantiatethedesignblock
ripple_carry_counterr1(q,clk,reset);
//Controltheclock
initialclk=1'b0;
always#5clk=~clk;

//Controlthereset
initial
begin
reset=1'b1;
#15reset=1'b0;
#180reset=1'b1;
#10reset=1'b0;
#20$stop;
end
//Monitortheoutputs
initial
$monitor($time,"Outputq=%d",q);
endmodule

The testbench generates the input stimulus

Observation of data is often included in the testbench

Data Values and Strengths

0, 1, X, Z

Reflect traditional digital logic values

Strengths from highZ -> supply

Used to resolve conflicts between drivers

Nets (Wires) and Registers

Nets represent physical connections between hardware elements
Declared with the keyword wire (or default for ports)
Used to connect instantiated modules
Must be continuously driven with a value
Ex. wireb,c;
Registers represent storage elements
Not necessarily physical registers but synthesis tools often assume that
Registers do not need to be continuously driven
Registers will hold a value until it is overwritten
Ex.
regreset;
initial
begin
reset=1b1;
#100reset=1b0;
end

Vectors
Nets and Registers can be declared as vectors
If no bitwidth is specified, 1 bit is assumed

wire[7:0]a;
reg[0:31]addr1,addr2;

Subsets of bits can be selected

addr1[2:0] = addr2[3:1];

Other Data Types

Verilog allows integers, real, and time types
Arrays can be made from other types
- Arrays can be multidimensional
- A vector is conceptually a single elements with many bits
- An array is many elements put together
wire[7:0]x;//avector
wirex[7:0];//anarray
wire[7:0]x[7:0];//anarrayofvectors
wirex[7:0][7:0];//atwodimensionalarray
Parameters are constants
parameterline_width=80;

System Tasks and Compiler Directives

Typically I/O tasks which require special simulator operations
System Tasks: $<keyword>, used at simulation time
- $display is a print statement in the code (like printf)
$display(Hello,world!);
- $monitor prints a signal value when it changes
$monitor(clock=%b,reset=%b,clock,reset);
- Only one $monitor statement can be active
- $monitoron, $monitoroff
Compiler Directives: <keyword>, used at compile time
- define creates macros (just like #define in C)
definex32
- include inserts entire verilog files (just like #include in C
includeheader.v

Dataflow Descriptions, Continuous Assignments

assignout=i1&i2;
Use the assign keyword (in most cases)
Left hand side must be a net of some kind (scalar or vector), not a register
Right hand side can be registers, nets, or function calls
Continuous assignments are always active. Execution hard to trace
They are evaluated whenever a right hand side operand changes value
Delays (inertial) can be added to represent component delays
assign#10out=i1&i2;
Continuous assignment can be implicit in a net declaration
wireout=i1&i2;

Continuous Assignment Example

moduleedge_dff(q,qbar,d,
clk,clear);
//Inputsandoutputs
outputq,qbar;
inputd,clk,clear;
//Internalvariables
wires,sbar,r,rbar,cbar;
//Makecomplementofclear
assigncbar=~clear;

//Inputlatches
assignsbar=~(rbar&s),
s=~(sbar&cbar&~clk),
r=~(rbar&~clk&s),
rbar=~(r&cbar&d);
//Outputlatch
assignq=~(s&qbar),
qbar=~(q&r&cbar);
endmodule

This is basically a structural description

Behavioral Modeling, Structured Procedures

Always blocks and initial blocks
- Parallel constructs: all blocks can execute in parallel
Initial blocks
- The block executes only once
- By default, starts at time 0 (but this can be changed)
- Often used for initialization
modulestimulus;
regx,y,a,b,m;
initial
begin
#5a=1'b1;
#25b=1'b0;
end

initial
begin
#10x=1'b0;
#25y=1'b1;
end
endmodule

Always Blocks
Always blocks
- The block executes in an infinite loop
- By default, starts at time 0 (but this can be changed)
- Represents a concurrent hardware block
- Needs a delay
moduleclock_gen;
regclock;
initial
clock=1'b0;
always
#10clock=~clock;
initial
#1000$finish;
endmodule

Procedural Statements, Blocking Assignments

Blocking Assignments
- Represented with a = sign
- All blocking assignments are executed in sequence
moduledummy;
regx,y,z;
reg[15:0]reg_a,reg_b;
integercount;
initial
begin
x=0;y=1;z=1;
count=0;
reg_a=16'b0;
reg_b=reg_a;
reg_a[2]=#151;
reg_b[15:13]=#10{x,y,z};
count=count+1;
end

Non-Blocking Assignments
Non-Blocking Assignments
- Represented with a <= sign
- All non-blocking assignments are executed in parallel
- Try not to mix with blocking assignments
moduledummy;
regx,y,z;
reg[15:0]reg_a,reg_b;
integercount;
initial
begin
x=0;y=1;z=1;
count=0;
reg_a=16'b0;
reg_b=reg_a;
reg_a[2]<=#151;
reg_b[15:13]<=#10{x,y,z};
count=count+1;
end

Delay and Event Control

Delay Statements
- Represented with a # sign
- Delays the execution of the statement immediately after
- Inertial delay model (ignores glitches)
- Additive with blocking statements
Event Control Statements
- Edge sensitive, represented with a @ sign
- Delays the execution until expression transitions
Ex. always @(clock)
always @(posedge clock)
always @(a or b)
- Level sensitive, represented with wait statement
Ex. always wait (enable) #20 cnt = cnt + 1;