EE603 CMOS IC DESIGN

Topic 5 CMOS Inverter

Lesson Learning Outcome

1)
a.
b.
c.
d.
e.

To explain the properties and performance of static

CMOS Inverter
CMOS Voltage Transfer Characteristic (VTC)
Switching Threshold
Noise Margin
Device Variation
Supply Voltage Scaling

2)
a.

To explain the dynamic behaviour of CMOS inverter

Parasitic Capacitances

Inverter Switch Models

When Vin is high and equal to VDD, the NMOS transistor is ON, while the
PMOS is OFF. A direct path exists between Vout and the ground node,
resulting in a steady-state value of 0V.
When the input voltage is low (0 V), NMOS transistor is OFF, while
PMOS transistors in ON. A direct path exists between VDD and Vout, resulting
in a steady-state value of VDD.

CMOS Properties
1. The voltage swing is equal to the supply voltage - output levels
high equal VDD and output levels low equal GND (Full rail-torail swing) high noise margins
2. The logic levels are not dependent upon the relative device
sizes, so that the transistors can be minimum size.
3. Low output impedance (output resistance in k range) which
makes it less sensitive to noise and disturbances.
4. Extremely high input resistance (MOS transistor gate is a
virtually perfect insulator and draws no dc input current.)
large fan-out.
5. No direct path exists between the supply and ground rails under
steady-state operating conditions no static power
dissipation.

NMOS & PMOS Operation in CMOS

NMOS & PMOS I-V Curve

NMOS & PMOS I-V Curve

Combining the VI characteristics
of the n-device and p-device

IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD
For a DC operating points to be valid, the
currents through NMOS and PMOS
devices must be equal.
The DC points are located at the
intersection of corresponding load lines,
as marked with dots on the graph.

CMOS Inverter VTC

CMOS Inverter VTC is produced from both

NMOS and PMOS IV curve.

CMOS INVERTER
Relative transistor sizing for better performance
of CMOS Inverter:
When designing static CMOS circuits, it is advisable
to balance the driving strengths of the transistors by
making the width of the PMOS two or three times
than the width of NMOS in order to obtain
symmetrical characteristics.
The impact : to maximize the noise margins.

For ideal symmetrical inverter required that:

CMOS INVERTER
Switching Threshold
Vout = Vin

VM

VM , The switching
threshold is defined as the
point where the
intersection of the VTC
curve and the line given by
Vout = Vin.
The switching threshold
voltage presents the
midpoint of the switching
characteristics.
A good inverter must
have the value VM = VDD/2
(to have comparable high
and low noise margins).

CMOS INVERTER
Noise Margin
By definition, VIH and VIL are
where dVout/dVin= -1 (= gain)
For typical inverter:
When : Vin =0, Vout = Vmax
Vin =VIL, Vout = VOH
Vin =VM, Vout = VM
Vin =VIH, Vout = VOL
Vin =VDD, Vout = Vmin

Typical inverter transfer characteristics

BUT, when Vin is between VIL and

VIH , Vout is in the transition region
where the logic level is undefined.

CMOS INVERTER

CMOS INVERTER

CMOS INVERTER
Effect of Transistor Size on VTC
If :

Effect on switching threshold:

VM= VDD/2, exactly in the middle.
Effect on noise margin:
VIH and VILboth are close to VM and
noise margin is good.

CMOS INVERTER
Impact of device variation on VTC Curve
The good transistor has:
smaller oxide thickness
smaller length
higher width
smaller threshold voltage
The bad transistor has:
larger oxide thickness
larger length
lower width
larger threshold voltage
Conclusion:
The variations cause a small shift
in the switching threshold, but that
the operation of the gate is not
affected.
Process variations (mostly) cause a
shift in the switching threshold.

CMOS INVERTER
Impact of device variation on VTC Curve
Result from changing (W/L)p / (W/L)n ratio:
Inverter threshold VM VDD/2
Rise and fall delays are unequal
Noise margins are not equal

CMOS INVERTER
Impact of supply voltage scaling

The inverter characteristic can still

be obtained although the supply
voltage is small (not even large
enough to turn the transistors on.)
How does this happen?
Because of sub-threshold operation
of the transistors.
The sub-threshold currents are
sufficient to switch the gate
between low and high levels, and
provide enough gain to produce
acceptable VTCs.
However, the very low value of the
switching currents will slow down
the operation of the transistor.

Impact of Supply Voltage Scaling

At around 100 mV, the gate

characteristic will deteriorate.
VOL and VOH are no longer at the
supply rails and the transitionregion gain approaches 1.
A digital circuit must achieve
sufficient gain to operate. So, it
is necessary that the supply must
be at least a few times the
thermal voltage.
Below this thermal voltage,
thermal noise will cause
unreliable operation.

CMOS Inverter : Dynamic Behaviour

The Switch Model of Dynamic CMOS Inverter

CMOS Inverter : Dynamic Behaviour

Parasitic Capacitances of CMOS inverter

Parasitic capacitances, influencing the transient behaviour of

the cascaded inverter pair.

CMOS Inverter : Dynamic Behaviour

Parasitic Capacitances Miller Effect

The Miller effect A capacitor that has identical but opposite

voltage swings at both its terminals can be replaced by a capacitor
to ground, whose value is two times the original value.

CMOS Inverter : Dynamic Behaviour

Sources of parasitic capacitance:
i. Intrinsic MOS transistor capacitances
ii.Extrinsic MOS transistor (fan-out) capacitances
iii.Wiring (interconnect) capacitance

Sources of Parasitic Capacitances

MOS Intrinsic Capacitances
Structure capacitances
Channel capacitances
Diffusion capacitances

Intrinsic Capacitances
MOS Structure Capacitance

Overlap Capacitance (linear):

CGSO = CGDO = Cox xd WL = Co WLD

Intrinsic Capacitances
Overlap Capacitance
In reality the gate overlaps
source and drain.
So, the parasitic overlap
capacitances:
CGS(overlap) = Cox W LD
CGD(overlap) = Cox W LD

Intrinsic Capacitances
MOS Channel Capacitances
The gate-to-channel capacitance depends upon the
operating region and the terminal voltages

Intrinsic Capacitances
MOS Channel Capacitances
Average Channel Capacitance

Intrinsic Capacitances
MOS Diffusion Capacitances
The junction (or diffusion) capacitance is from the
reverse biased source-body and drain-body p-n
junctions.

Intrinsic Capacitances
Source Junction View

Extrinsic Capacitance
Extrinsic (Fan-out) Capacitance
The extrinsic, or fanout, capacitance is the total gate
capacitance of the loading PMOS and NMOS transistors.
Cfanout = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn + CGDOn + WnLnCox) +
(CGSOp + CGDOp + WpLpCox)
Simplification of the actual situation
Assumes all the components of Cgate are between Vout and
GND (or VDD)

Assumes the channel capacitances of the loading gates are

constant

MOS Capacitance Model

Summary
1. When designing static CMOS circuits, the width of PMOS
must be made two or three times than the width of NMOS
in order to obtain symmetrical switching threshold, VM and
noise margin.
2. The variations of NMOS and PMOS in CMOS cause a small
shift in the switching threshold, but that the operation of the
gate is not affected.
3. The inverter characteristic can still be obtained although the
supply voltage is scaled down, as long as the minimum
supply voltage is higher than thermal voltage
4. Parasitic capacitances slower the switching speeds
=>Bigger capacitance means more charges are needed to change
voltage.

Past Years Questions

1. a) Sketch a complete CMOS inverter circuit diagram.
(2 marks)
2. Explain the CMOS inverter operation.
(2 marks)
3. Based of the Voltage Transfer Characteristics (VTC) curve
below, explain the transition region when both NMOS and
PMOS are in saturation.
(5 marks)