INTRODUCTION TO

CMOS VLSI
DESIGN

SRAM

OUTLINE
Memory Arrays
SRAM Architecture

SRAM Cell
Decoders
Column Circuitry
Multiple Ports

Serial Access Memories

CMOS VLSI Design

SRAM

Slide 2

MEMORY ARRAYS

Memory Arrays

Random Access Memory

Read/Write Memory
(RAM)
(Volatile)

Static RAM
(SRAM)

Dynamic RAM
(DRAM)

Mask ROM

Programmable
ROM
(PROM)

Content Addressable Memory

(CAM)

Serial Access Memory

Read Only Memory

(ROM)
(Nonvolatile)

Shift Registers

Serial In
Parallel Out
(SIPO)

Erasable
Programmable
ROM
(EPROM)

Queues

Parallel In
Serial Out
(PISO)

Electrically
Erasable
Programmable
ROM
(EEPROM)

First In
First Out
(FIFO)

Last In
First Out
(LIFO)

Flash ROM

CMOS VLSI Design

SRAM

Slide 3

ARRAY ARCHITECTURE
2n words of 2m bits each bitline conditioning
wordlines

If n >> m, fold by 2k into fewer rows of more

bitlinescolumns
row decoder

n-k
n

memory cells:
2n-k rows x
2m+k columns

column
circuitry

k
column
decoder

2m bits

Good regularity easy to design

Very high density if good cells are used
CMOS VLSI Design
SRAM

Slide 4

12T SRAM CELL

Basic building block: SRAM Cell
Holds one bit of information, like a latch
Must be read and written

12-transistor (12T) SRAM cell

Use a simple latch connected to bitline
46 x 75 unit
bit cell
write
write_b
read
read_b

CMOS VLSI Design

SRAM

Slide 5

6T SRAM CELL
Cell size accounts for most of array size
Reduce cell size at expense of complexity

6T SRAM Cell
Used in most commercial chips
Data stored in cross-coupled inverters

Read:

bit

bit_b

word

Precharge bit, bit_b

Raise wordline

Write:
Drive data onto bit, bit_b
Raise wordline
CMOS VLSI Design
SRAM

Slide 6

SRAM READ
Precharge both bitlines high
Then turn on wordline

bit_b

bit
word

P1 P2
One of the two bitlines will be pulled down byN2 the
cell N4
A

Ex: A = 0, A_b = 1

A_b
N1 N3

bit discharges, bit_b stays high

But A bumps up slightly

A_b

bit_b

1.5

Read stability

1.0

A must not flip

bit

word

0.5

A
0.0
0

100

200

300
time (ps)

400

500

600

CMOS VLSI Design

SRAM

Slide 7

SRAM READ
Precharge both bitlines high
Then turn on wordline

bit_b

bit
word

P1 P2
One of the two bitlines will be pulled down byN2 the
cell N4
A

Ex: A = 0, A_b = 1

A_b
N1 N3

bit discharges, bit_b stays high

But A bumps up slightly

A_b

bit_b

1.5

Read stability

1.0

A must not flip

N1 >> N2

bit

word

0.5

A
0.0
0

100

200

300
time (ps)

400

500

600

CMOS VLSI Design

SRAM

Slide 8

SRAM WRITE
Drive one bitline high, the other low
Then turn on wordline

bit_b

bit
word

Bitlines overpower cell with new value

P1 P2

N2
A

A_b
N1 N3

Ex: A = 0, A_b = 1, bit = 1, bit_b = 0

Force A_b low, then A rises high

A_b
A

1.5

Writability

N4

bit_b

Must overpower feedback inverter

1.0

0.5

word

0.0
0

100

200

300

400

500

600

700

time (ps)

CMOS VLSI Design

SRAM

Slide 9

SRAM WRITE
Drive one bitline high, the other low
Then turn on wordline

bit_b

bit
word

Bitlines overpower cell with new value

P1 P2

N2
A

A_b
N1 N3

Ex: A = 0, A_b = 1, bit = 1, bit_b = 0

Force A_b low, then A rises high

A_b
A

1.5

Writability

N4

bit_b

Must overpower feedback inverter

N2 >> P1

1.0

0.5

word

0.0
0

100

200

300

400

500

600

700

time (ps)

CMOS VLSI Design

SRAM

Slide 10

SRAM SIZING
High bitlines must not overpower inverters during
reads
bit_b

bit

But low bitlines must write new value into cell

word

weak
med

med
A

A_b
strong

CMOS VLSI Design

SRAM

Slide 11

SRAM COLUMN EXAMPLE

Bitline Conditioning

Bitline Conditioning

Read

Write

More
Cells

More
Cells

word_q1

word_q1

SRAM Cell

bit_b_v1f

out_b_v1r

bit_v1f

bit_b_v1f

bit_v1f

SRAM Cell

write_q1

out_v1r

data_s1
1
2
word_q1
bit_v1f
out_v1r

CMOS VLSI Design

SRAM

Slide 12

SRAM
LAYOUT
Cell size is critical: 26 x 45 (even smaller in industry)
Tile cells sharing VDD, GND, bitline contacts

GND

BIT BIT_B GND

VDD

WORD

Cell boundary

CMOS VLSI Design

SRAM

Slide 13

DECODERS
n:2n decoder consists of 2n n-input AND gates
One needed for each row of memory
Build AND from NAND or NOR gates
A1

A0

A1

Static CMOS

Pseudo-nMOS

word0
word1

A0

A1

A0

word

word0
word1

word2

word2

word3

word3

1/2
A0

A1

16

word

CMOS VLSI Design

SRAM

Slide 14

DECODER LAYOUT
Decoders must be pitch-matched to SRAM cell
Requires very skinny gates
A3

A3

A2

A2

A1

A1

A0

A0

VDD

word

GND
buffer inverter

NAND gate

CMOS VLSI Design

SRAM

Slide 15

LARGE DECODERS
A3 gates
A2
A1 become
A0
For n > 4, NAND
slow

Break large gates into multiple smaller gates

word0

word1

word2

word3

word15

CMOS VLSI Design

SRAM

Slide 16

PREDECODING
A3

Many of these gates are redundant

A2

Factor out common

gates into predecoder
Saves area
Same path effort

A1

A0

predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3

word15

CMOS VLSI Design

SRAM

Slide 17

COLUMN CIRCUITRY
Some circuitry is required for each column
Bitline conditioning
Sense amplifiers
Column multiplexing

CMOS VLSI Design

SRAM

Slide 18

BITLINE CONDITIONING

Precharge
bitlines
high before reads
bit
bit_b

Equalize bitlines
to minimize voltage difference when

using sense amplifiers

bit

bit_b

CMOS VLSI Design

SRAM

Slide 19

SENSE AMPLIFIERS
Bitlines have many cells attached
Ex: 32-kbit SRAM has 256 rows x 128 cols
128 cells on each bitline

tpd (C/I) V
Even with shared diffusion contacts, 64C of diffusion capacitance
(big C)
Discharged slowly through small transistors (small I)

Sense amplifiers are triggered on small voltage swing

(reduce V)

CMOS VLSI Design

SRAM

Slide 20

DIFFERENTIAL PAIR AMP

Differential pair requires no clock
But always dissipates static power
sense_b
bit

P1

P2

N1

N2

sense
bit_b

N3

CMOS VLSI Design

SRAM

Slide 21

CLOCKED SENSE AMP

Clocked sense amp saves power
Requires sense_clk after enough bitline swing
bit
bit_b
Isolation transistors
cut off
large bitline capacitance
isolation
transistors

sense_clk

regenerative
feedback

sense

sense_b

CMOS VLSI Design

SRAM

Slide 22