8086 Microprocessor

It is a 16 bit p.
8086 has a 20 bit address bus can access upto
220 memory locations ( 1 MB) .
It can support upto 64K I/O ports.
It provides 14, 16-bit registers.
It has multiplexed address and data bus

Architecture of 8086
Internal Block Diagram of 8086
Internal block diagram can be partitioned
to 2 parts
Bus Interface Unit (BIU)
Execution Unit(EU)

8086 Internal Architecture

M e m o ry
In te rfa c e

EU - Execution Unit
General Purpose Registers

In te rn a l b u s

B IU

Pointer Registers
Index Registers
ALU

5
5

In te rn a l
bus

4
ES

SS
D S

BIU-Bus Interface Unit

CS

Flags

Segment Registers

IP
C o n tro l S y s te m
EU

CS, DS, ES, SS, IP

In te rn a l B u s

Queue

Memory Addressing
Segment Base
Offset

A H

A L:

BH

BL

CH

CL

D H

D L

A LU

SP
BP
SI

O p e ra n d s

D I

F la g s

Q ueue

EU & BIU
The 8086 CPU logic has been partitioned into two functional
units namely Bus Interface Unit (BIU) and Execution Unit (EU)
The major reason for this separation is to increase the
processing speed of the processor
The BIU has to interact with memory and input and
output devices in fetching the instructions and data required
by the EU
EU is responsible for executing the instructions of the
programs and to carry out the required processing

EXECUTION UNIT
Decodes instructions fetched by the BIU
Generate control signals,
Executes instructions.

The main parts are:

Control Unit
Internal bus
ALU
Registers
5

Execution Unit
Control unit is responsible for the co-ordination of
all other units of the processor
ALU performs various arithmetic and logical
operations over the data
The

instruction

decoder

translates

the

instructions fetched from the memory into a

series of actions that are carried out by the EU

EXECUTION UNIT General Purpose Registers

16 bits

AX
BX
CX
DX

8 bits

8 bits

AH

AL

BH

BL

Base

CH

CL

Count

DH

DL
SP

Pointer

BP
SI

Index

DI

Accumulator

Data
Stack Pointer
Base Pointer
Source Index
Destination Index
7

General Purpose Registers

Each of these 16-bit registers are
further subdivided into two 8-bit
registers.
AX

AH

AL

BX

BH

BL

CX

CH

CL

DX

DH

DL
8

General Purpose Registers

AX Register: AX register is also known as
accumulator register that stores operands for
arithmetic operation like divided, rotate.

BX Register: This register is mainly used as a

base register. It holds the starting base location
of a memory region within a data segment.

CX Register: It is defined as a counter. It is

primarily used in loop instruction to store loop
counter.

DX Register: DX register is used to contain

I/O port address for I/O instruction.
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Execution Unit Registers

General registers are used for temporary storage
and manipulation of data and instructions
Accumulator

register

consists

of

two

8-bit

registers AL and AH, which can be combined

together and used as a 16-bit register AX
Accumulator can be used for I/O operations and
string manipulation

Execution Unit Registers

Base register consists of two 8-bit registers BL and BH,
which can be combined together and used as a 16-bit
register BX
BX register usually contains a data pointer used for based,
based indexed or register indirect addressing
Count register consists of two 8-bit registers CL and CH,
which can be combined together and used as a 16-bit
register CX
Count register can be used as a counter in string
manipulation and shift/rotate instructions

Execution Unit Registers

Data register consists of two 8-bit registers DL
and DH, which can be combined together and
used as a 16-bit register DX
Data register can be used as a port number in I/O
operations
In integer 32-bit multiply and divide instruction
the DX register contains high-order word of the
initial or resulting number

Execution Unit Registers

Pointer & Index Register

(1). Stack Pointer (SP),
(2). Base Pointer (BP),
(3). Source Index (SI),
(4). Destination Index (DI).

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Pointer & Index Register

Following Registers can also be used as a general Purpose
Registers.
(1).Stack Pointer (SP) is a 16-bit register pointing to program Stack, also
contains 16-Bit offset address.
(2).Base Pointer (BP) is a 16-bit register pointing to data in stack
segment. BP register is usually used for based indexed or register
indirect addressing.
(3).Source Index (SI) is a 16-bit register used for indexed, based indexed
and register indirect addressing, as well as a source data address in
string manipulation Instructions
(4).Destination Index (DI) is a 16-bit register used for indexed, based
indexed and register indirect addressing, as well as a destination data
address in string manipulation instructions.
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EXECUTION UNIT Flag Register

A flag is a flip flop which indicates some conditions produced by
the execution of an instruction or controls certain operations of
the EU .
In 8086 The EU contains
a 16 bit flag register
9 of the 16 are active flags and remaining 7 are undefined.
6 flags indicates some conditions- status flags
3 flags control Flags
U

Over flow

O
F

Direction

U - Unused

D
F

IF

TF SF ZF U

Interrupt Trap

Sign

A
F

PF U

Auxiliary
Zero

Parity

CF
Carry

16

Auxiliary Carry Flag

Flag Register

Carry Flag

This is set, if there is a carry from the

lowest nibble, i.e, bit three during
addition, or borrow for the lowest
nibble,
i.e,
bit
three,
during
subtraction.

This flag is set, when there is

a carry out of MSB in case of
addition or a borrow in case
of subtraction.

Sign Flag

Zero Flag

Parity Flag

This flag is set, when the

result of any computation
is negative

This flag is set, if the result of

the computation or comparison
performed by an instruction is
zero

This flag is set to 1, if the lower

byte of the result contains even
number of 1s ; for odd number
of 1s set to zero.

15

14

13

12

11

10

OF

DF

IF

TF

SF

ZF

Over flow Flag

This flag is set, if an overflow occurs, i.e, if the result of a signed

operation is large enough to accommodate in a destination
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set.

Direction Flag

This is used by string manipulation instructions. If this flag bit

is 0, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto incrementing mode.

4
AF

2
PF

0
CF

Trap Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize
external mask interrupts; clearing IF
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disables these interrupts.

BUS INTERFACE UNIT

(BIU)

Contains
6-byte Instruction Queue (Q)
The Segment Registers (CS, DS, ES, SS).
The Instruction Pointer (IP).
The Address Summing block ()

18

BIU Instruction Byte

Queue
8086 instructions vary from 1 to 6 bytes
Therefore fetch and execution are taking place
concurrently in order to improve the performance
of the microprocessor
The BIU feeds the instruction stream to the
execution unit through a 6 byte prefetch queue

BIU Instruction Byte

Queue
Execution and decoding of certain instructions do not
require the use of buses
While such instructions are executed, the BIU fetches up
to six instruction bytes for the following instructions
(the subsequent instructions)
The BIU store these prefetched bytes in a first-in-first out
register by name instruction byte queue
When the EU is ready for its next instruction, it simply
reads the instruction byte(s) for the instruction from the
queue in BIU

Instruction Pointer
The Instruction Pointer (IP) in 8086 acts as a Program
Counter.

It points to the address of the next instruction to be

executed.

Its

content

is

automatically

incremented

when

the

execution of a program proceeds further.

The contents of the IP and Code Segment Register are
used to compute the memory address of the instruction
code to be fetched.
This is done during the Fetch Cycle.

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Segmented
Memory

The memory in an 8086/88 based

Physical Memory
00000

system is organized as segmented

Code segment (64KB)

memory.
The CPU 8086 is able to address
1Mbyte of memory.

Extra segment (64KB)

The Complete physically available

Stack segment (64KB)

memory may be divided into a

number of logical segments.

1 MB

Data segment (64KB)

FFFFF
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Segment: Offset
Notation
The total addressable memory size is 1MB
Most of the processor instructions use 16-bit
pointers the processor can effectively address
only 64 KB of memory

To access memory outside of 64 KB the CPU uses

special segment registers to specify where the
code, stack and data 64 KB segments are
positioned within 1 MB of memory

Segment Registers
There are four segment registers in Intel 8086:
(1). Code Segment Register (CS),
(2). Data Segment Register (DS),
(3). Stack Segment Register (SS),
(4). Extra Segment Register (ES).

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Segment Register
A segment register points to the starting
address of a memory segment.
For e.g.:
The code segment register points to the starting
address of the code segment.
The data segment register points to the starting
address of the data segment, and so on.

The maximum capacity of a segment may be

up to 64 KB.
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Segment Register
Code segment (CS): It is a 16-bit register containing address of 64 KB
segment with processor instructions.
The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP)
register.
CS register cannot be changed directly. The CS
register is automatically updated
jump, far call and far return instructions

during

far
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Segment Register
Stack segment (SS): It is a 16-bit register containing address of 64KB

segment with program stack.

By default, the processor assumes that all data

referenced by the stack pointer (SP) and base

pointer (BP) registers is located in the stack
segment.
SS register can be changed directly using POP

instruction.

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Segment Register
Data segment (DS): It is a 16-bit register containing address of 64KB
segment with program data.
By default, the processor assumes that all data
referenced by general register BX and index
register (SI, DI) is located in the data segment.

28

Segment Register
Extra segment (ES): It is a 16-bit register containing address of 64KB
segment, usually with program data.
By default, the processor assumes that the DI
register references the ES segment in string
manipulation instructions.

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Summary of Registers & Pipeline of 8086

P
BIU

EU
AX

AH

AL

BX

BH

BL

CX

CH

CL

DX

DH

DL

SP
BP
SI

IP
D
E
C
O
D
E
R

QUEUE

CS

DS

ES

SS

IP

BX
DI

DI

SP
BP

SI

DI
FLAGS

ALU

Timing
control

Default Assignment

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