ROA LOGIC

FPGA TO ASIC MIGRATION

Technology Migration
Technology Migration is the process of the moving from one
hardware or operating Environment to another for the basis of
optimization.
The following slides will talk about using RISC V has a means
for FPGA and ASIC optimization.
Market conditions dictate freely migrating between these
technologies is highly desirable
E.g. price pressure, power reduction, ASIC EOL, security

Current Problems with FPGA

Current trends present in the market right now :
FPGAs: prototyping, low volume, no NRE, fast TTM
Platform ASIC: high performance, low power, fast TTM
Std.cell ASICs: highest performance, lowest power, lowest
unit price
FPGA Vendor specific macros limit the migration to another
vendor/technology.
Most notably FPGA vendor provided CPUs (e.g. Nios,
Microblaze) restrict their usage in other technologies.
FPGAs are quite expensive thus migration helps in price
reduction.

Current Problems with FPGA

We need to take care about the power requirements as the
systems can be in isolated spaces .
Protection
-IP theft by copying bit stream .
-Security breach by snooping bit stream or hijacking FPGA .
FPGAs are having some performance limits thus we have to
switch to other technologies.

How RISC V helps

Many alternative sources proprietary and open source are
available :
1. ARM, MIPS, ARC
2.OpenRisc, Leon 2/3
3.OpenSparc, T1

However all these options have limitataions

less ROI as high upfront cost are incurred.
No platform portability. Designed specifically for ASIC or
FPGA.
Outdated ISAs.

How RISC V helps

CPU requirements
Royalty free
Target technology independent
Equally well suited for FPGA and ASIC
Low resource requirements
Flexible instruction/feature set
Support for multiple bus interfaces
The RISC-V ISA allows us to fulfill all of the above

RISC V Specifications
ROA adopted RISC V integer set as their base with operation
ability on both 32 and 64bit machines.
They called it RV11.
1. RV11 = in-order execution with single instruction issue.
.Folded optimizing, 5 stage Pipeline
ID stage decides if instruction sequence can be optimized.
Improves IPC by hiding stalls
.Migration ability
Parameters allows trade offs between features, ISA extensions,
and performance vs. area
Flexible bus interface allows virtual drop-in into any existing
system

Architecture

Case Study
Replaced an existing NIOS II CPU working on an Altera
Cyclone V with ASIC migration
Specifications:
100 DMIPS
No MMU , No Caches
AHB3 bus incorporated .

Implementation Results
Logic Cells

Flip-flops

bRAM

Fmax

Power

Cyclone-V

1923 ALMs

1561

114MHz

556mW

Nextreme-3

7924 eCells

2386

649MHz

170mW

14721 eCells

4249

578MHz

221mW

64bit

Nextreme-3 chosen for price, performance, and power because it

provides good results and almost 5.7x performance increase while
reducing power by 70%

Summary and Conclusions

Implementing RISC-V in a technology independent manner by
successfully replacing existing FPGA CPU can give a higher
optimization on various levels .
Results :
Successfully migrated FPGA to Platform ASIC thereby
improving CPU performance by 5x and power by 70%
Future steps include :
Improve resource utilization
Increase extensions offerings
Add multi-threading, multi-issue (already in work RV22)

LOW RISC Project

Introduction
lowRISC is creating a fully open-sourced, Linux-capable,
RISC-V-based SoC, that can be used either directly or as the basis
for a custom design.
It is based for the operators or customers to base their derivative
designs on this open project chip.
They call it as LINUX of Hardware world.
Focus areas includes Flexibility and Security on the open source
SoC .

Projects in 2015
1. Tagged Memory
2. Untethered SoC

Tagged Memory
Tagged memory associates metadata with each
memory location and can be used to implement finegrained memory access restrictions. Attacks which
hijack control flow can be prevented by using this
protection to restrict writes .

Tagged Memory
Motivation: security and other applications
-An end to control-flow hijacking attacks .
-Flexible security policies. Also uses for debug, performance
monitoring.
The implementation of tagged memory presented here
provides only basic support by extending on-chip caches to
hold tags and by adding a tag cache.
Instruction set support is provided for testing in the form of
load and store tag (ltag, stag) instructions.

Tagged Memory
The bare minimum changes required for a tagged memory
system to work are:
Instructions to get and set memory tags.
A modified compiler which will tag every code pointer and
verify the tag is still present when loading it. The function
prologue and epilogue will set and clear the tag on the return
address.
Modifications to the memory allocator to clear the tags upon
freeing an allocation.

Untethered SoC
Working to provide a standalone or untethered SoC for Rocket Chip. Cores
in the original Rocket chip rely on communicating with a companion processor
via the host-target interface (HTIF) to access peripherals and I/O.
This release removes this requirement, adding an I/O bus and instantiating
FPGA peripherals which can boot RISC V Linux.

lowRISC in 2016
Kernel changes in Untethered SoC foe a better performance. The
new additions may include porting new libraries in the system.
Replace FPGA vendor-provided IP with vendor-neutral ones
also helping in FPGA migration in future cases.
Interrupt controller .

BERI PIC to be used as a base for this which is another project

out from Cambridge. Acts as an intermediate standard .

Test Chip 2016

3mm x 3mm 28nm die, wire-bond BGA package
4 cores (evaluating BOOM), each with 32KiB Instruction + Data $
BERI PIC, tagged memory, run-control + trace debug, RV64G+C
512KiB shared L2 and 128KiB tag cache
LPDDR3 memory controller + PHY, 32-bit wide
8 Minion cores with 500MHz+ clock. Provide SDHC, SPI, I2C,
I2S, UART
USB 2.0 host PHY and controller

Test Chip 2016 Architecture

Why
firewalls?

Further Implementations
Re-integrate tagged memory.
Integrate minion cores . This may include adding new
scalable cores for more advanced functionalities.
Shim implementation .
Integration of third-party IP
Benchmarking and performance analysis

A 32-bit 100MHz RISC-V

Microcontroller with
10-bit SAR ADC in 130nm CMOS GP

Introduction
Initial :
An ARM-M0 to be used as on-chip test platform for
high-speed interfaces. Test of high-speed flops and
circuitry within a processor.
Current:
A low-footprint RISC-V microcontroller alike EFM32
(Silicon Labs) and SAMD11 (Atmel) with USB lowspeed PHY on-chip.

Reference Inputs