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Communicating with I/O

To perform a read or write operation to an I/O device, the


processor must perform several I/O operations. For example it has
to know the I/O status of the device before performing the
requested operation. Therefore the I/O operations may be
performed by either one of 2 methods:

1. Polling:
It is the simplest way for communicating with I/O.
In this method the processor checks the status of each I/O
device periodically to know if the device needs to be served
or not.
If the device has a serving request, the processor performs
the request and then checks the status of the next device and
so on.

The disadvantage of this method is that a lot of processor


time may be wasted in the interrogation process.

Example to determine the impact of polling overhead:


Assume that the number of clock cycles for polling operations
is 100 and the processor runs with 50 MHz clock. Determine
the percentage CPU time consumed for the following cases,
assuming that polling time is enough so that no data is ever
lost:
a. The mouse must be polled 30 times/s,
b. The floppy disk transfers data in words (2 bytes) and has
data rate of 50 Kbyte/s.
c. The hard disk transfers data in double word (4 bytes) and
has data rate of 2 Mbyte/s.

Solution:
a. For mouse:
Clock cycles per second for polling = 30 x 100 =3000 C/s
Percentage time of CPU = 3000/(50 x 10 6) = 0.006%
Polling for mouse can be used without much performance
impact on the CPU.
b. For Floppy Disk:
The polling rate = 50 x 210 / 2 = 25 x 210 polling /s
Percentage time of CPU = 25 x 210 x 100/(50 x 106) = 5%
Polling for Floppy disk can be used with a reasonable
performance impact on the CPU.

c. For Hard Disk:


The polling rate = 2 x 220 / 4 = 512 x 210 polling /s
Percentage time of CPU = 512 x 210 x 100/(50 x 106)
= 105%
Which means that the CPU will be completely consumed by
polling the hard disk. This means that polling cannot be used
in hard disk.
Therefore another way must be used with fast devices to
decrease the I/O access time required by polling.

2. Interrupt-Driven I/O:
This method is used by almost all systems for at least some
devices.
In this case, the device employs I/O interrupts to indicate to
the CPU that it needs servicing and sends its ID to inform
the CPU which device requests servicing.
The processor uses this ID to jump to the location
associated with this ID in an area of the memory called
Interrupt Vector to get the address of the Interrupt Service
Routine ISR of this device.
The processor then jump to the ISR using this address to
perform device service.

Effect of interrupt on the previous example:


Assuming the overhead for each transfer using interrupt is 100
cycles,
a. For mouse:
the percentage of the processor time consumed during a
transfer will be similar to polling = 0.006%.
b. For Floppy Disk:
The percentage of the processor time consumed during a
transfer is similar to polling = 5%. The advantage of
interrupt is that the CPU will not be disturbed when the disk
is idle. If the floppy is only active for 10% of the time, then :
Processor time consumed during a transfer = 5 * 0.1= 0.5%

This means that interrupt decreases the CPU time consumed by


floppy transfer.
c. For hard disk :
the CPU time consumed will not decrease because the CPU
is involved all the time. Thus a new mechanism should be
used for higher bandwidth devices. The Direct Memory
Access Controller (DMAC) is used to perform this transfer
directly between Memory and I/O.

Direct Memory Access (DMA)


* DMA techniques improve system performance
* External devices can transfer data directly to or
from memory under hardware control
* DMA is used when very high data rates are
required

Code to Move Data From Input to


Memory
READ_BYTE:

IN
MOV
INC
DEC
JNZ

AL, DX
[BX], AL
BX
CL
READ_BYTE

[13]
[2]
[2]
[2]
[10]

This Code takes 29 clock cycles


At 20MHz:
fclk = 20MHz; Tclk = 1/fclk = 50ns; 29 x 50ns = 1450ns =
1.45us per byte

1/(1.45us/B) = 670KB/s (slow)


DMA could achieve 10MB/s at the same clock frequency

DMA Structure
Address Bus

Address Bus
Buffer

Channel 0
Address Register

Data Bus

Data Bus
Buffer

CS

Word Count Register

DREQ
DACK

Control Register

IOR
IOW
MR

Channel 1

MW
HREQ
HACK

Channel 2

DREQ
DACK
DREQ
DACK

DMA Modes of Operations


1. Single Word transfer mode:
Where the DMA transfers one word only in each transfer.
2. Block mode:
Where the DMA transfers a block of words in each transfer.

DMAC Signals
Address Bus (I/O and O + T)
IOR(I/O + T),
MR(O + T),
HREQ(O),
DREQ(I),
CS(I)

Data Bus(I/O + T),


IOW(I/O+T),
MW(O + T),
HACK(I),
DACK(O),

DMA Phases
* DMA Works in 2 phases
1. Programming Phase
Where the CPU treats DMAC as I/O. The CPU gives the DMAC
complete information about the requested data transfer (block size,
direction, memory address and I/O channel).

2. Bus master Phase


Where DMAC starts executing I/O commands by:

a. Requesting the bus from CPU by activating Bus Request


signal (HOLD).
b. Starting execution of the requested transfer after receiving
Bus Grant signal (HLDA).
c. Releasing the bus to the CPU at the end of transfer.

DMA Interfacing
DREQ

HOLD

CPU
Address Data R W IOR IOW

CS
HLDA

Address
Decoder

DMAC

Address Data

Data W

RAM

IOR

R W

IOW

DACK

R
CS

Decoder

I/O
Device
Data IOR IOW

MEMORY
DEVICE
(including
DECODER)

Address Bus

Data Bus

MPU

MEMR#
MEMW#
IOR#
IOW#

MEMR#
MEMW#
IOR#
IOW#

DMA
INTR
INTA

I/O DEVICE
HOLD
HLDA

DREQ
DACK

DMA Transfer (MO)


Address Bus

Data Bus

MPU

MEMR#
MEMW#
IOR#
IOW#

MEMR#
MEMW#
IOR#
IOW#

DMA
INTR
INTA

I/O DEVICE
HOLD
HLDA

DREQ
DACK

MEMR# and IOW# Active


Data Transfer from
Memory to Output

Data Transfer in this


direction

MEMORY
DEVICE
(including
DECODER)

DMA Timing (MO)


DREQ

HOLD
HLDA
DACK
ADDRESS

address n

address n+1

IOW

MEMR

DATA

valid

valid

DMA Transfer (IM)


MEMORY
DEVICE
(including
DECODER)

Address Bus

MPU

Data Transfer in this


direction

Data Bus

MEMR#
MEMW#
IOR#
IOW#

MEMR#
MEMW#
IOR#
IOW#

DMA
INTR
INTA

I/O DEVICE
HOLD
HLDA

DREQ
DACK

MEMW# and IOR# Active


Data Transfer from Input
to Memory

DMA Timing (IM)


DREQ

HOLD

HLDA

DACK

ADDRESS

address n

address n+1

IOR

MEMW

DATA

valid

valid

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