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1. Polling:
It is the simplest way for communicating with I/O.
In this method the processor checks the status of each I/O
device periodically to know if the device needs to be served
or not.
If the device has a serving request, the processor performs
the request and then checks the status of the next device and
so on.
Solution:
a. For mouse:
Clock cycles per second for polling = 30 x 100 =3000 C/s
Percentage time of CPU = 3000/(50 x 10 6) = 0.006%
Polling for mouse can be used without much performance
impact on the CPU.
b. For Floppy Disk:
The polling rate = 50 x 210 / 2 = 25 x 210 polling /s
Percentage time of CPU = 25 x 210 x 100/(50 x 106) = 5%
Polling for Floppy disk can be used with a reasonable
performance impact on the CPU.
2. Interrupt-Driven I/O:
This method is used by almost all systems for at least some
devices.
In this case, the device employs I/O interrupts to indicate to
the CPU that it needs servicing and sends its ID to inform
the CPU which device requests servicing.
The processor uses this ID to jump to the location
associated with this ID in an area of the memory called
Interrupt Vector to get the address of the Interrupt Service
Routine ISR of this device.
The processor then jump to the ISR using this address to
perform device service.
IN
MOV
INC
DEC
JNZ
AL, DX
[BX], AL
BX
CL
READ_BYTE
[13]
[2]
[2]
[2]
[10]
DMA Structure
Address Bus
Address Bus
Buffer
Channel 0
Address Register
Data Bus
Data Bus
Buffer
CS
DREQ
DACK
Control Register
IOR
IOW
MR
Channel 1
MW
HREQ
HACK
Channel 2
DREQ
DACK
DREQ
DACK
DMAC Signals
Address Bus (I/O and O + T)
IOR(I/O + T),
MR(O + T),
HREQ(O),
DREQ(I),
CS(I)
DMA Phases
* DMA Works in 2 phases
1. Programming Phase
Where the CPU treats DMAC as I/O. The CPU gives the DMAC
complete information about the requested data transfer (block size,
direction, memory address and I/O channel).
DMA Interfacing
DREQ
HOLD
CPU
Address Data R W IOR IOW
CS
HLDA
Address
Decoder
DMAC
Address Data
Data W
RAM
IOR
R W
IOW
DACK
R
CS
Decoder
I/O
Device
Data IOR IOW
MEMORY
DEVICE
(including
DECODER)
Address Bus
Data Bus
MPU
MEMR#
MEMW#
IOR#
IOW#
MEMR#
MEMW#
IOR#
IOW#
DMA
INTR
INTA
I/O DEVICE
HOLD
HLDA
DREQ
DACK
Data Bus
MPU
MEMR#
MEMW#
IOR#
IOW#
MEMR#
MEMW#
IOR#
IOW#
DMA
INTR
INTA
I/O DEVICE
HOLD
HLDA
DREQ
DACK
MEMORY
DEVICE
(including
DECODER)
HOLD
HLDA
DACK
ADDRESS
address n
address n+1
IOW
MEMR
DATA
valid
valid
Address Bus
MPU
Data Bus
MEMR#
MEMW#
IOR#
IOW#
MEMR#
MEMW#
IOR#
IOW#
DMA
INTR
INTA
I/O DEVICE
HOLD
HLDA
DREQ
DACK
HOLD
HLDA
DACK
ADDRESS
address n
address n+1
IOR
MEMW
DATA
valid
valid