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Local and Metroplitan Area

Networks
(I-7000)

Professor Tarek Saadawi


Rm 529
X7263
Office Hours: Thursday 12 1:30
Also random in Tuesday

Introduction to Digital/Data Communications Systems


I(t)
Input

x(t)
Transmitter

channel

r(t)

~I(t)
Receiver

Output
Device

Code [ A
1000001]
Encode
Modulation, amplification, Fitering
Fig 1 Basic Model For a Communication System
I (t) =

Analog
Digital

X (t) =

Analog
Digital

-----------------------------------------------------------------------------

----------------------------------------------------------------------------0
1

1
Receiver with
Fast Clock

x
x
x

-----------------------------------------------------------------------------

Transmitted
signal

-----------------------------------------------------------------------------

-----------------------------------------------------------------------------

-----------------------------------------------------------------------------

0
1
0
0

0
1

x
x

x
x
x

0
Receiver with
Slow Clock

Figure 2.6 Problems caused by Clock Drift

Time
Transmitter
Clock

ASYNCHRONOUS
Serial

Parallel

SYNCHRONOUS

20 mA current loop
EIA RS 232C
EIA RS-422, 423, 499
EIA RS 485

BISYNC
HDLC
ISDN LAP-d
IEEE 802 standards
_

IEEE STD 488 1978

Microprocessor
Interfaces
_

Figure 2.9 Typical data transfer interfaces

Bit stream to be
transmitted b(t)

Encoder

transmitted signal
d(t)
transmission link

b(t)

Decoder

Figure 2.10 bits are encoded digital signaling


Bit stream to be
transmitted b(t)

Modulator

transmitted signal
a(t)
transmission link

b(t)

Demodulator

Figure 2.11 bits are modulated into analog signaling

Bit stream to
be transmitted
+v
0

RZ

-v
+v

Leads to out of
synch, DC voltage,

NRZ
-v

Differential encoding;
comparing the polarity of
adjacent bits, more reliable

to detect a transition than


to compare a threshold

NRZ1
Self-clocking, 2 symbols per
bit (baud), 10 Mbps means 20
MBauds, =50%

Manchester

-v

Bit stream to
be transmitted
Differential
Manchester

Alternating Mark
Inversion
3-levels, binary zero
is zero voltage,
binary 1 alternates

Duo binary
1 = previous 1 if even
zeros, otherwise the
complement

Figure 2.12
Reasons for line coding: Freq spectrum; freq spectrum, synchronization, better performance under noisy environment

0
b(t)

A1 cos(wt + )
A2 cos(wt + )

b(t) = 1
b(t) = 0
N

(a) ASK

A cos (2f t + )

frequency
f1
(b) FSK

frequency
f2
(c) PSK

1800 phase
shift

A cos (2f1 t + )b(t)


A cos (2f2 t + )b(t)

1800 phase
shift
A cos (2f1 t + )b(t)
A cos (2f2 t +1800 )
b(t) = 0

Figure 2.14 Digital Signal Modulation Techniques

b(t)

multiplication
X

Carrier

Q PSK
x(t)
A cos (wt + 0 )
A cos (wt + 90 )
A cos (wt + 180 )
A cos (wt + 2 )
M-ary PSK

b(t)
00
01
11
10

Mary PSK:
x(t) = A con ( 2ft + { 2f2 / M } ) ,
M=2
M=4

PSK
QPSK

Type of signal
Information
transmitted
to be transmitted
Anolog

Digital

k = 0,1,.., M.

Anolog

Digital

AM, FM, PM Modulator


(transmitter) Anolog

PCM, Delta Modulator

ASK, PSK, FSK, MSK


RZ, NRZ, NRZ1
(Moderns)
codec, Digital transmitter

Figure 2.16 Example of Information Signaling format


and the devices used.

Input
(10011)

G0 = 1
+

G2 = 1

G1 = 0
A

Shift Register G(X) = X3 + X2 + 1


r=3

XOR
0 0 0
0 1 1
1 0 1
1 1 0
Shift Register
Content

Step
0
1
2
3
4
5
6
7
8

Input A
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0

B
0
0
1
1
0
1
1
0
1

C
0
0
0
1
0
0
1
0
0

G3 = 1