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CP323L1
Advanced Logic Circuit
Engr. Rommel A. Manalo,
CpE Department
Introduction to VHDL
VHDL is a language for describing digital
Verilog
Essentially identical in function to VHDL
No generate statement
programming
Open Verilog International Standard
Example Code:
dataflow
Concurrent
statements
structural
behavioral
(sequential)
Levels of Design
Description
VHDL Fundamentals
Fundamental parts of a
LIBRARY
Case Sensitivity
VHDL is not case sensitive
Example:
Names or labels
databus
Databus
DataBus
DATABUS
Identifiers
Basic identifiers are made up of alphabetic,
Reserved Keywords:
Examples:
Identify the legal identifiers
_tx_clk?
Examples:
Select?
if (a=b) then
or
if (a=b) then
or
if (a =
b) then
are all equivalent
VHDL Comments
Comments in VHDL are indicated with a double
dash, i.e., --
Comment indicator can be placed anywhere in the
line
Any text that follows in the same line is treated as a
comment
Carriage return terminates a comment
No method for commenting a block extending over a
couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus;
FIFO
VHDL Comments
Explain function of module to other
designers
Explanatory, not just restatement of code
Locate close to code described
Put near executable code, not just in a
header
Logic Operators
Logic operators
and
or
nand
nor
xor
not
xnor
or
not
nand
nor
xor
xnor
No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
VHDL operators
VHDL Code
Example: NAND Gate
VHDL Code
3 sections to a piece of VHDL code
File extension for a VHDL file is .vhd
Name of the file is usually the entity name
(nand_gate.vhd)
Fundamental Part Of A
Library
Library is a collection of commonly used
Library Declarations
Design Entity
Entity Declaration
Entity Declaration describes the interface
Port Mode IN
Architecture
Entity describes the ports of the module
Architecture describes the functionality of
Architecture Simplified
Syntax
(inputs, outputs)
Architecture describes the behavior of the
model
Can have multiple architectures for one
entity
STD_LOGIC
a
1
wire
b
8
bus
10
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a:
b:
c:
d:
Splitting buses
a
4
10
5
b
c
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a:
b:
c:
d:
A Sample Model(1)
Description
Implementation
A Sample Model(2)
Description
Implementation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC
);
END xor3;
VHDL Statements
VHDL has a reputation as a complex
concurrent statements.
Each concurrent statement will synthesize to a block
of logic.
Another class of VHDL statements are called
sequential statements.
Sequential statements can ONLY appear inside of a
process block.
A process block is considered to be a single
concurrent statement.
Can have multiple process blocks in an architecture.
Usually use process blocks to describe complex
combinational or sequential logic.
(same as before).
process).
The sensitivity list should contain any signals that appear on the
right hand side of an assignment (inputs) or in any boolean for a
sequential control statement.
The if statement condition must return a boolean value (TRUE
if-else statement
if-else statement
Analysis on Unassigned
Output
In the above process, the ELSE clause was left out. If the
if-elsif-else statement
Example: Priority circuit
Priority circuit has 7 inputs; Y7 is highest
Priority
Circuit
using if-elsifelse
statement
Analysis on Priority
Example
This is the first example that used a bus. The DOUT signal is
2-to-1 Multiplexer
s
w
0
w
1
w
0
w
1
: IN
: OUT
STD_LOGIC ;
STD_LOGIC ) ;
w
2
0
w
1
y
1
s2
s1
4 x 1 Multiplexer
s
0
s
1
w
w
w
w
s s
1 0
00
01
10
11
0
1
2
3
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
simple selection.
The synthesis tool has to work harder than
necessary to understand that all possible
choices for sel are specified and that no
priority is necessary.
Just want a simple selection mechanism.
adder.
Logic equation for each full adder is:
sum <= a xor b xor ci;
co <= (a and b) or (ci and (a or b));
library ieee;
use ieee.std_logic_1164.all;
entity adder4bit is
port ( a,b: in std_logic_vector(3 downto 0);
cin : in std_logic;
cout: out std_logic;
sum: out std_logic_vector(3 downto 0)
);
end adder4bit;
architecture bruteforce of adder4bit is
-- temporary signals for internal carries
signal c : std_logic_vector(4 downto 0); .
begin
process (a, b, cin, c)
begin
-- full adder 1
sum(1) <= a(1) xor b(1) xor c(1);
c(2) <= (a(1) and b(1)) or (c(1) and (a(1) or b(1)));
-- full adder 2
sum(2) <= a(2) xor b(2) xor c(2);
c(3) <= (a(2) and b(2)) or (c(2) and (a(2) or b(2)));
-- full adder 3
sum(3) <= a(3) xor b(3) xor c(3);
c(4) <= (a(3) and b(3)) or (c(3) and (a(3) or b(3)));
cout <= c(4);
end process;
end bruteforce;
Straight forward implementation. Nothing wrong with
Analysis on for-loop
statement
The for-loop can be used to repeat blocks of
logic
The loop variable i is implicity declared for
this loop; does not have to be declared
anywhere else.
To visualize what logic is created, 'unroll'
the loop by writing down each loop
iteration with loop indices replaced hard
numbers.
Summary
There are many different ways to write
Summary (Cont.)
This course is about Digital System DESIGN, not