Lesson 1

CPLDs and FPGAs: Technology and

Design Features

Sept. 2005

EE37E Adv. Digital

Electronics

Topics

Fundamental Concepts
CPLDs vs FPGAs
CPLD Architectures
FPGA Architectures
Design Methods for FPGA-based Systems
Intellectual Property
System-on-chip
Reconfigurable Computing
Future FPGA Developments
Sept. 2005

EE37E Adv. Digital

Electronics

1. Fundamental Concepts
What are CPLDs and FPGAs?
Complex Programmable Logic Devices (CPLDs) and
Field Gate Arrays (FPGAs) are digital integrated
circuits (ICs) that contain configurable
(programmable) blocks of logic along with
configurable interconnects between these blocks.
Design engineers can configure (program) such
devices to perform a tremendous variety of tasks

Sept. 2005

EE37E Adv. Digital

Electronics

Classification of Digital ICs

Sept. 2005

EE37E Adv. Digital

Electronics

They thing about CPLDs and FPGAs:

The thing that really distinguish an FPGA or a CPLD from an
ASIC is the programmable feature.
Let us consider a simple programmable function:

Sept. 2005

In order to make our function more

interesting, we need some
mechanism that allows us to establish
one or more of the potential links.
EE37E Adv. Digital
Electronics

Fusible link technology

These fuses are similar in to

household fuses.
Sept. 2005

EE37E Adv. Digital

Electronics

Programmed fusible links

Devices based on fusible-link technologies are said

to be one-time programmable, or OTP. FPGAs dont
use them.

Sept. 2005

EE37E Adv. Digital

Electronics

Antifuse Technologies
Antifuse links are an alternative to fuse links.
An antifuse link is programmable by applying a
voltage across it.
An antifuse is given as follows:

Sept. 2005

EE37E Adv. Digital

Electronics

Other Technologies

EPROM
EEPROM
FLASH
SRAM

Sept. 2005

EE37E Adv. Digital

Electronics

2. CPLDs vs. FPGAs

CPLD
architecture

PLDs = PALs, PLAs,or GALs

Small number of PLDs on a single chip

Programmable interconnect between PLDs
Sept. 2005

EE37E Adv. Digital

Electronics

FPGA architecture

Much larger number of

smaller programmable logic blocks.
Embedded in a sea of lots and lots
of programmable interconnect.

Sept. 2005

EE37E Adv. Digital

Electronics

3. CPLD Architectures

Identical individual PLD blocks (Xilinx FBs) replicated in different

family members.
Different number of PLD blocks
Different number of I/O pins
Many CPLDs have fewer I/O pins than macrocells
Buried Macrocells -- provide needed logic terms internally but
these outputs are not connected externally.
IC package size dictates # of I/O pins but not the total # of
macrocells.
Typical CPLD families have devices with differing resources in
the same IC package.

Sept. 2005

EE37E Adv. Digital

Electronics

Xilinx CPLDs

Notice overlap in resource availability in a particular package.

Sept. 2005

EE37E Adv. Digital

Electronics

Xilinx 9500-family CPLD architecture

72 ==>
XC9572

Sept. 2005

EE37E Adv. Digital

Electronics

9500-family function blocks (FBs)

18 macrocells per FB
36 inputs per FB (partitioning challenge, but also reason for relatively
compact size of FBs)
Macrocell outputs can go to I/O cells or back into switch matrix to be
routed to this or other FBs.

Sept. 2005

EE37E Adv. Digital

Electronics

9500-series macrocell (18 per FB)

Set control
Programmable
inversion or XOR
product term
Up to 5 product
terms

Global clock or
product-term
clock
Reset control

OE control
Sept. 2005

EE37E Adv. Digital

Electronics

9500-series product-term allocator

programmable
steering
elements

Sept. 2005

Share terms from

above and below

EE37E Adv. Digital

Electronics

9500-series I/O block

Sept. 2005

EE37E Adv. Digital

Electronics

Switch matrix for XC95108

Could be anything from a limited set of multiplexers to a full

crossbar.
Multiplexer -- small, fast, but difficult fitting
Crossbar -- easy fitting but large and slow
Sept. 2005

EE37E Adv. Digital

Electronics

XC9500 Product Family

9536

9572

95108

95144

95216

95288

Macrocells

36

72

108

144

216

288

Usable Gates

800

1600

2400

3200

4800

6400

tPD (ns)

7.5

7.5

7.5

10

10

Registers

36

72

108

144

216

288

Max I/O

34

72

108

133

166

192

PC84
TQ100
PQ100
PQ160

PQ100
PQ160

Packages

Sept. 2005

VQ44
PC44

PC44
PC84
TQ100
PQ100

EE37E Adv. Digital

Electronics

PQ160
HQ208
BG352

HQ208
BG352

CoolRunner-II
CoolRunner-II Family
Lowest system cost using advanced
features
Lowest power
High speed
Additional security
Smallest packages
Including worlds smallest low cost package - QF32

1.5V, 1.8V, 2.5V & 3.3V interface

2 to 4 I/O banks

Sept. 2005

EE37E Adv. Digital

Electronics

CoolRunner-II CPLD Architecture

AIM: Advanced Interconnect Matrix

Sept. 2005

EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics