Lesson 4

Synchronous Design Architectures:

Data Path and High-level Synthesis
(part two)

Sept. 2005

EE37E Adv. Digital

Electronics

Topics
Data Subsystem.
High-level Synthesis
Scheduling
Allocation

Sept. 2005

EE37E Adv. Digital

Electronics

1. Data Subsystem
It consists of:
Storage modules, such registers;
Functional modules (operators);
Buses, composed of switches and wires connecting
storages and functional modules;
Control points, which are points where control signals
are connected; and
Condition points, which are corresponding to output
signals used by the control subsystem.

Sept. 2005

EE37E Adv. Digital

Electronics

1.2 Example of a data subsystem

Sept. 2005

EE37E Adv. Digital

Electronics

1.2. Storage Elements

Storage modules provide storage for data and
conditions. The basic storage module is a
register; a data subsystem usually contains
several of them. These registers can be
organized as:
INDIVIDUAL REGISTERS, with separate connections
and controls;
ARRAYS OF REGISTERS, sharing connections and
controls;
REGISTER FILE
RANDOM-ACCESS MEMORY (RAM)

COMBINATION OF INDIVIDUAL REGISTERS AND

ARRAYS OF REGISTERS.
Sept. 2005

EE37E Adv. Digital

Electronics

Register File

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Register File Description

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EE37E Adv. Digital

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Functional Modules
Functional Modules (operators) perform
transformations on bit-vectors.
An operator is specified by the names of input
and output vectors, and the name of the function
performed by the operator.
Operators can perform several operations as
specified by operation-selection inputs.

Sept. 2005

EE37E Adv. Digital

Electronics

CASE op_sel IS
WHEN F1 => z_out <= x_in op1 y_in AFTER delay;
WHEN F2 => z_out <= x_in op2 y_in AFTER delay;
....
END CASE;

Figure: Functional Module (Operator)

Sept. 2005

EE37E Adv. Digital

Electronics

Buses
Buses provide connection between components
in the system. They consist of:
Direct connections, also called wires, links, or lines;
and
Switches to enable the connections.

Sept. 2005

EE37E Adv. Digital

Electronics

Figure: EXAMPLES OF DATAPATHS: a) unidirectional dedicated datapath (serial); b)

bidirectional dedicated datapath (parallel);
c) shared datapath (bus).

Sept. 2005

EE37E Adv. Digital

Electronics

Switches are requires to enable paths in a shared bus; these

switches are implemented by three-state gates or by selectors.

Figure: Vector gate switches

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EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

Type of buses
Complete connection, called crossbar, in which
m simultaneous transfers are possible.
Single interconnection, which allows only one
source to be connected at the bus at a time.

Sept. 2005

EE37E Adv. Digital

Electronics

Figure: Crossbar connection

Sept. 2005

EE37E Adv. Digital

Electronics

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EE37E Adv. Digital

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EE37E Adv. Digital

Electronics

Sept. 2005

EE37E Adv. Digital

Electronics

2. High-level Synthesis
High-level synthesis also know as behavioral
synthesis constructs a register-transfer from a
behavior in which the times of operations are not
fully specified.
High-level synthesis methods help us
understand the design space and come up with
a design that meets all our requirements.
This technique is particularly useful in FPGA
Rapid Prototyping.
The primary jobs in translating a behavior
specification into architecture are scheduling and
allocation (binding).
Sept. 2005

EE37E Adv. Digital

Electronics

 A program that models a chips desired function

is given a variety of names: functional model,
behavioral model, architectural simulator, to
name few.
A specification program mimics the behavior of
the chip at its pins.
The internal of the specification need have
nothing to do with how the chip works, but the
input/output behavior of the behavior model
should be the same as that of the chip.

Sept. 2005

EE37E Adv. Digital

Electronics

 Sequential operation is not the most abstract

description of behavior.
We can describe behavior without assigning
operations to particular clock cycles.
High-level synthesis (behavioral synthesis)
transforms an unscheduled behavior into a
register-transfer behavior.

Sept. 2005

EE37E Adv. Digital

Electronics

Tasks in high-level synthesis

Scheduling: determines clock cycle on which
each operation will occur.
Allocation: chooses which function units will
execute which operations.

Sept. 2005

EE37E Adv. Digital

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Functional modeling code in Verilog

O1 <= i1 or i2;
if (i3 =b(0)) then
o1 <= b(1);
o2 = a + b;
else
o1 = b(0);
end;

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What distinguishes it from a registertransfer description is that the cycles on

which these operations are to occur are
not specifies.

EE37E Adv. Digital

Electronics

Data dependencies
Data dependencies describe relationships
between operations:
x <= a + b; value of x depends on a, b

High-level synthesis must preserve data

dependencies.
Data flow constrains are critical for scheduling
and allocation.
The most natural model of computation that
expresses the data flow process is the data flow
graph (DFG).
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EE37E Adv. Digital

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Data flow graph

Data flow graph (DFG) models data
dependencies.
Does not require that operations be performed in
a particular order.
Models operations in a basic block of a
functional modelno conditionals.
Requires single-assignment form.

Sept. 2005

EE37E Adv. Digital

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Data flow graph construction

original code:
x <= a + b;
y <= a * c;
z <= x + d;
x <= y - d;
x <= x + c;

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single-assignment form:
x1 <= a + b;
y <= a * c;
z <= x1 + d;
x2 <= y - d;
x3 <= x2 + c;

EE37E Adv. Digital

Electronics

Data flow graph construction, contd

Data flow forms directed acyclic graph (DAG):

Sept. 2005

EE37E Adv. Digital

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Goals of scheduling and allocation

Preserve behaviorat end of execution, should
have received all outputs, be in proper state
(ignoring exact times of events).
Utilize hardware efficiently.
Obtain acceptable performance.

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EE37E Adv. Digital

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Data flow to data path-controller

One feasible schedule for last DFG:

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EE37E Adv. Digital

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Binding values to registers

registers fall on
clock cycle
boundaries

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Register lifetimes
a

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EE37E Adv. Digital

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Allocation creates multiplexers

Same unit used for different values at different
times.
Function units.
Registers.

Multiplexer controls which value has access to

the unit.

Sept. 2005

EE37E Adv. Digital

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Choosing function units

muxes allow
function units
to be shared
for several
operations

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EE37E Adv. Digital

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Building the sequencer

sequencer requires three states,

even with no conditionals
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VHDL for data path

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EE37E Adv. Digital

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Choices during high-level synthesis

Scheduling determines number of clock cycles
required; binding determines area, cycle time.
Area tradeoffs must consider shared function
units vs. multiplexers, control.
Delay tradeoffs must consider cycle time vs.
number of cycles.

Sept. 2005

EE37E Adv. Digital

Electronics

Finding schedules
Two simple schedules:
As-soon-as-possible (ASAP) schedule puts every
operation as early in time as possible.
As-late-as-possible (ALAP) schedule puts every
operation as late in schedule as possible.

Many schedules exist between ALAP and ASAP

extremes.

Sept. 2005

EE37E Adv. Digital

Electronics

ASAP and ALAP schedules

ASAP

ALAP

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EE37E Adv. Digital

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VHDL model of ASAP schedule

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EE37E Adv. Digital

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VHDL of ALAP schedule

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EE37E Adv. Digital

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Critical path of schedule

Longest path through data flow determines
minimum schedule length:

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EE37E Adv. Digital

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Operator chaining
May execute several operations in
sequence in one cycleoperator
chaining.
Delay through function units may
not be additive, such as through
several adders.

Sept. 2005

EE37E Adv. Digital

Electronics