Delta Sigma

Modulation

Data Converters
Two Types:
Nyquist rate DC
fs

2fin ; Resolution is 8 12 bits; SNR is poor

Over sampled DC
fs

>> 2fin ; Resolution is 16 30 bits; SNR is good

OSR = fs/2fin

SNR = 6.02N + 1.76

=> N (ENoB) = (SNR 1.76)/ 6.02

Over Sampled Data Converters

Approach:
Delta Sigma modulation and demodulation
Delta Sigma ADC

DS modulator
The DS modulator is the heart of the DS ADC. It is

responsible for digitizing the analog input signal and

reducing noise at lower frequencies.
In this, the architecture implements a function called

noise shaping that pushes low frequency noise up to

higher frequencies where it is outside the band of
interest.
Noise shaping is one of the reasons that DS converters

are well-suited
measurements.

for

low-frequency,

For example: Bio-Medical applications

high

accuracy

Block Diagram of ADC

DS modulator

DS modulator
The output of DS modulator is like a PWM.
Delta-sigma modulation converts the analog voltage into a pulse

frequency and is alternatively known as Pulse Density modulation or

Pulse Frequency modulation.

OSR values
like 64, 128 ie., in step of 2n
For example
Choose QSR 128; fin = 20 KHz

=> fs = 5.12 MHz 5 MHz

Integrator
Analog Filter
High performance filter is needed.

Low power and area, High speed,

Less noise

OTA
Opamp. = OTA + Buffer

Integrator has to act as a low pass filter for signal and high

pass filter for noise.

Vout/Vin = [1/(s+1) + s/(s+1)]

(signal + noise)
Architectures of OTA

DS ADC

DS ADC

DS ADC
Higher order modulators
SNR increses
Stability to be taken care

Follow different approach

For example:

For implementing 5th order = second order + second order +

first order

Higher Resolution
Higher bits
Have a parallel comparators/ quantizers
Instead of 1 bit, have 4 1 bit comparator/
quantizers
For generating higher bits like 16 bits

Have a decompressed digital filter

Like adder doing 3:2 compression, do decompression.

N-1 comparators are required to generate n

levels.

DS modulator
OSR values
like 64, 128 ie., in step of 2n
For example
Choose QSR 128; fin = 20 KHz

=> fs = 5.12 MHz 5 MHz

DS modulator

DS modulator
OSR values
like 64, 128 ie., in step of 2n
For example
Choose QSR 128; fin = 20 KHz

=> fs = 5.12 MHz 5 MHz

Decimation filters
Decimation filters have employed multirate

and multistage architectures resulting in

simple hardware which minimize filter wordlengths, eliminate the need of multipliers and
reduce the number of registers required.
Since the decimation filter operates at very
high sampling rate, the multistage filter chain
uses simpler filtering blocks in the initial
stages to reduce power.

Block Diagram of Decimator

SINC4 FILTER
A SINC filter, also called the Moving Average
Filter, averages N samples. More stop band
attenuation is obtained by cascading the
SINC. The transfer function of an N tap SINC
filter is,

A SINC filter has its nulls at fs/N where N is the

number of taps and fs is the sampling
frequency.

SINC4 Filter implementation,

Retimed, Pipelined Hogenauer
structure

Decimation Filter
An

economical hardware implementation of a

multistage decimation filter can be done using
Cascaded Integrator Comb filter (CIC) with the
transfer function
where N is the oversampling ratio and k is the order
of the filter (k=3).
Figure 1 shows the direct implementation of
decimation filter. Since the whole circuit is working at
sampling frequency, fs (fs=N. Nyquist rate ) the
power consumption of the circuit is high.

IIR FIR Structure

A simplified implementation of CIC filter is shown in

Fig. 2.
In this circuit, the IIR filters work at fs and the FIR
filter works at Nyquist rate (fN).
So the power consumption of this architecture is
reduced significantly. Moreover the area is reduced
due to the reduction of registers and adders.
To avoid register overflow the word length of the IIR
filter should be b+k.log2N, where b is the length of
the output of modulator (here b = 1).

Thank you
G. Lakshminarayanan