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Introduction
Credits:
Slides adapted from:
J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006
C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004
N.H.E. Weste, D. Harris, CMOS VLSI Design, 3/e, Prentice Hall, 2004
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Design
process of coming up with a solution to a problem
Digital Systems
transform signals that can be abstracted as discrete in range and domain
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CLK
Sequential
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1= 0=
ON OFF
=1 =0
OFF ON
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charging
Capacitors
hold charge
capacitance
Resistors
resistance
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Packaged Chips
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Types of ICs
ASSP
ASIC
Full-custom
Semi-custom
Cell Based
Gate Arrays
Programmable
CPLD
and FPGA
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RTL
SW
Abstraction
RTL
System Level
Gate Level
Register
Transfer Level
(HDL)
Transistor Level
1970
1980
1990
2000+
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Z = A S + B S
1
S
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Moores Law
In 1963 Gordon Moore predicted that as a result of continuous miniaturization
transistor count would double every 18 months
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Transistors become smaller, faster, consume less power, and are
cheaper to manufacture
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CAD Tools
Logic
Design
Design Entry
Schematic capture
Hardware Description Languages
Logic Synthesis
Pre layout verification
Functional simulation
Formal methods
Timing Analysis
Floorplanning
Placement
Physical
Routing
Design
Extraction
Post layout verification
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