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Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross
section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the
range of 0.02 to 0.1 m.
Recent trend: more and more analog circuits are implemented in MOS technology for
lower cost integration with digital circuits in a same chip
Physical Operation
of Enhancement MOSFET
Physical Operation of
Enhancement MOSFET
Applying a Small vDS
Applying a small vDS (~ 0.1 or 0.2 V) causes a
current iD to flow through the induced nchannel
from D to S.
The magnitude of iD depends on the density of
electrons in the channel, which in turn depends on
vGS.
For vGS = Vt (threshold voltage), the channel is
just induced and the conducted current is still
negligibly small.
As vGS > Vt, depth of the channel increases, iD
will be proportional to (vGS Vt), known as
excess gate voltage or effective voltage.
Increasing vGS above Vt enhances the channel,
hence it is called enhancement type MOSFET.
Note that iG=0.
Physical Operation of
Enhancement MOSFET
Operation as vDS is Increased
v DSsat v GS V t
v DSsat v GS V t
Physical Operation of
Enhancement MOSFET
v DSsat
v GS V t
v DSsat
v GS V t
The drain current iD versus the drain-to-source voltage vDS for an enhancement-type
NMOS transistor operated with vGS > Vt.
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a
conductance whose value is determined by vGS. Specifically, the channel conductance
is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the
depletion region is not shown (for simplicity).
iD 0.0004
iD
vGS Vt vDS
v DS
rDS
iD
Vt 1
4
K 5 10
rDS 500
v GS Vt 4
A
2
Triode Region
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is
formed in a separate n-type region, known as an n well. Another arrangement is
also possible in which an n-type body is used and the n device is formed in a p
well.
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with
the normal directions of current flow indicated. (b) The iD - vDS characteristics for
a device with Vt = 1 V and kn(W/L) = 0.5 mA/V2.
Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly
away from the drain, thus reducing the effective channel length (by L).
1
2
k' n
v GS V t
1 v DS
2
Exercise 5-4
Refer to exercise 5-3
a)
kn 20
iD kn
W 100
W
L
L 10
( vGS Vt ) vDS
1
2
vGS 3
vDS
iD 75
b)
nCox 20
1
W
2
iD nCox ( vGS Vt )
2
L
iD 100
c)
1
W
2
iD nCox ( vGS Vt )
2
L
iD 100
Vt 2
vDS 0.5
Exercise 5-5
For
iD
vDS 3
1
2
nCox
For
iD
iD
nCox
W
L
W
L
vGS vDS
( vGS Vt )
2
1
2
2 1
vGS 4
1
iD 1
nCox
vDS 5
W
L
( vGS Vt )
2 ( vGS Vt )
iD 4
W
L
[ ( vGS Vt ) vDS]
vDS
iD
1
[ 2 ( ( vGS Vt ) ) ]
rDS 0.25
Vt 2
The depletion type MOSFET has similar structure to that the enhancement type
MOSFET but with one important difference:
The depletion MOSFET has a physically implanted channel. Thus an n-channel
depletion-type MOSFET has an n-type silicone region connecting the source
and drain (both +n) at the top of the type substrate. Thus if a voltage vDS is
applied between the drain and source, a current iD flows for vGS = 0 i.e there
is no need to induce the channel.
The channel depth and hence its conductivity is controlled by vGS. Applying a
positive vGS enhances the channel by attracting more electrons. The reverse
when applying negative volt. The negative voltage is said to deplete the
channel (depletion mode).
The current-voltage
characteristics of a
depletion-type nchannel MOSFET for
which Vt = -4 V and
kn(W/L) = 2 mA/V2
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET Circuits at DC
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier
MOSFET As An Amplifier
Exercise - 5.22
W
kn
L
Vt 2
0.5
RG 1000000
ID 0.001
VGS 10
given
1
0.5 VGS 2
2
Find VGS 4
VG 0
RS
VS 4
4 ( 10)
VDmin
RS 6 10
ID
VG Vt
Thus
RD
10 0
ID
RD 1 10
Fig. 5.31 Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.
Fig. 5.33 Total instantaneous voltages vGS and vD for the circuit in Fig. 5.31.
Fig. 5.34 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation
effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
g mb
Fig. 5.37 the T model of the MOSFET augmented with the drain-to-source resistance ro.
gm
2 2 f VSB
Ro
V O
I O
r o2
V A2
IO
Fig. 5.42 Output characteristic of the current source in Fig. 5.40 and the current mirror of Fig. 5.41 for the case Q2 is matched to Q1.
Fig. 5.45 The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to
determine the transfer characteristic; and transfer characteristic.
Fig. 5.47 The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit
in (b).
Fig. 5.48 The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
Fig. 5.52 (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer
characteristic.
Fig. 5.53 The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic;
and (c) transfer characteristic.
Fig. 5.54 Small-signal equivalent circuit of the depletion-load amplifier of Fig. 5.43 (a), incorporating the body effect of Q 2.
Fig. 5.55 (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.
Fig. 5.56 Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction
to determine the operating point; and (c) equivalent circuit.
Fig. 5.57 Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
Fig. 5.59 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of
the operating point as the input goes high and C discharges through the Q N; (d) equivalent circuit during the capacitor discharge.
Fig. 5.65 Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) v A is positive; (b)
vA is negative.
Fig. 5.67 (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected
to the substrate (body); (c) the equivalent circuit model of (b) with C db neglected (to simplify analysis).