Lecture 7:

Power

Activity Factor Estimation

Activity factor: probability that a node switches 01
Define probability Pi that a node is 1
Probability that a node is 0 is then Pi = 1-Pi
i = Pi * Pi
Completely random data has P = 0.5 and = 0.25
Data is often not completely random
Data propagating through ANDs and ORs has lower
activity factor
Depends on design, but typically 0.1

7: Power

CMOS VLSI Design 4th Ed.

Switching Probability

7: Power

CMOS VLSI Design 4th Ed.

Example
A 4-input AND is built out of two levels of gates
Estimate the activity factor at each node if the inputs
have P = 0.5
NAND: If A and B are ones there will be a 0 output: PNAND=1-PAPB
NOR: If n1 and n2 are zeroes there will be a 1 output: PNOR=P1P2

NAND
NOR
NAND

7: Power

CMOS VLSI Design 4th Ed.

ON and OFF Current

Ion = Ids @ Vgs = Vds = VDD
Saturation

Ioff = Ids @ Vgs = 0, Vds = VDD

Cutoff

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Dominant source in contemporary transistors
Gate leakage
Tunneling through ultrathin gate dielectric
Junction leakage
Reverse-biased PN junction diode current

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Leakage
What about current in cutoff?
Simulated results
What differs?
Current doesnt
go to 0 in cutoff

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

DIBL
Electric field from drain affects channel
More pronounced in small transistors where the
drain is closer to the channel
Drain-Induced Barrier Lowering
VVV
Drain voltage also affect Vt
ttds

Vt Vt Vds
High drain voltage causes current to increase.

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Threshold Voltage Effects

Vt is Vgs for which the channel starts to invert
Ideal models assumed Vt is constant
Really depends (weakly) on almost everything else:
Body voltage: Body Effect
Drain voltage: Drain-Induced Barrier Lowering
Channel length: Short Channel Effect

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Body Effect
Body is a fourth transistor terminal
Vsb affects the charge required to invert the channel
Increasing Vs or decreasing Vb increases Vt
Vt Vt 0

s Vsb s

s = surface potential at threshold

s 2vT ln

NA
ni

Depends on doping level NA

And intrinsic carrier concentration ni

= body effect coefficient

tox
2q si N A
ox

4: Nonideal Transistor Theory

2q si N A
Cox

CMOS VLSI Design 4th Ed.

10

Body Effect
Body is a fourth transistor terminal
Vsb affects the charge required to invert the channel
Increasing Vs or decreasing Vb increases Vt
Vt Vt 0

s Vsb s

s = surface potential at threshold

s 2vT ln

NA
ni

Depends on doping level NA

And intrinsic carrier concentration ni

= body effect coefficient

tox
2q si N A
ox

4: Nonideal Transistor Theory

2q si N A
Cox

CMOS VLSI Design 4th Ed.

11

Body Effect Cont.

For small source-to-body voltage, treat as linear

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

12

Gate Leakage
Carriers tunnel thorough very thin gate oxides
Exponentially sensitive to tox and VDD

A and B are tech constants

Greater for electrons
So nMOS gates leak more
From [Song01]

Negligible for older processes (tox > 20 )

Critically important at 65 nm and below (tox 10.5 )
4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

13

Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt 0 Vds k Vsb

I ds I ds 0 e

1 e

nvT

Vds
vT

n is process dependent
typically 1.3-1.7
Rewrite relative to Ioff on log scale

S 100 mV/decade @ room temperature

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

14

Subthreshold Leakage
For Vds > 50 mV

I sub I off 10

Vgs Vds VDD k Vsb

S

Ioff = leakage at Vgs = 0, Vds = VDD

7: Power

Typical values in 65 nm
Ioff = 100 nA/m @ Vt = 0.3 V
Ioff = 10 nA/m @ Vt = 0.4 V
Ioff = 1 nA/m @ Vt = 0.5 V
= 0.1
k = 0.1
S = 100 mV/decade

CMOS VLSI Design 4th Ed.

15

Stack Effect
Series OFF transistors have less leakage
Vx > 0, so N2 has negative Vgs
Vx VDD Vx VDD k Vx

Vx VDD
S

S
I sub I off 10
I off 10
1 44 2 4 43 1 4 4 44 2 4 4 4 43
N1

Vx

N2

VDD
1 2 k
1 k

VDD

I sub I off 10

1 2 k

I off 10

VDD
S

Leakage through 2-stack reduces ~10x

Leakage through 3-stack reduces further
7: Power

CMOS VLSI Design 4th Ed.

16

NAND3 Leakage Example

100 nm process
Ign = 6.3 nA
Igp = 0
Ioffn = 5.63 nA

Ioffp = 9.3 nA

Data from [Lee03]

7: Power

CMOS VLSI Design 4th Ed.

17

Lecture 10:
Circuit
Families
CMOS VLSI Design 4th Ed.

Outline
Pseudo-nMOS Logic
Dynamic Logic
Pass Transistor Logic

10: Circuit Families

CMOS VLSI Design 4th Ed.

19

Introduction
What makes a circuit fast?
I = C dV/dt -> tpd (C/I) V
low capacitance
high current
small swing
Logical effort is proportional to C/I
pMOS are the enemy!

4
1

High capacitance for a given current

Can we take the pMOS capacitance off the input?
Various circuit families try to do this
10: Circuit Families

CMOS VLSI Design 4th Ed.

20

Pseudo-nMOS
In the old days, nMOS processes had no pMOS
Instead, use pull-up transistor that is always ON
In CMOS, use a pMOS that is always ON
Ratio issue
Make pMOS about effective strength of
pulldown network
1.8
1.5

load

P/2

1.2
P = 24

Ids

Vout 0.9

Vout
16/2
Vin

0.6
P = 14
0.3

P=4

0
0

0.3

0.6

0.9

1.2

1.5

1.8

Vin

10: Circuit Families

CMOS VLSI Design 4th Ed.

21

Dynamic Logic
Dynamic gates uses a clocked pMOS pullup
Two modes: precharge and evaluate

2
1

2/3

Static

4/3

Pseudo-nMOS

Precharge

Dynamic
Evaluate

Precharge

10: Circuit Families

CMOS VLSI Design 4th Ed.

22

The Foot
What if pulldown network is ON during precharge?
Use series evaluation transistor to prevent fight.

precharge transistor
Y

inputs

inputs
f

foot
footed

10: Circuit Families

CMOS VLSI Design 4th Ed.

unfooted

23

Monotonicity
Dynamic gates require monotonically rising inputs
during evaluation

0 -> 0
A
0 -> 1
1 -> 1
violates monotonicity
But not 1 -> 0
during evaluation
A

Precharge

Evaluate

Precharge

Y
Output should rise but does not

10: Circuit Families

CMOS VLSI Design 4th Ed.

24

Monotonicity Woes
But dynamic gates produce
monotonically falling
outputs during evaluation
Illegal for one dynamic gate
to drive another!
A=1

Precharge

Evaluate

Precharge

X
X monotonically falls during evaluation
Y
Y should rise but cannot

10: Circuit Families

CMOS VLSI Design 4th Ed.

25

Domino Gates
Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate
Produces monotonic outputs

domino AND

Precharge

Evaluate

Precharge

A
B

Y
Z

dynamic static
NAND inverter

A
B

10: Circuit Families

H
C

CMOS VLSI Design 4th Ed.

A
B

26

Charge Sharing
Dynamic gates suffer from charge sharing

Y
CY

B=0

Cx

A
Y
Charge sharing noise
x

CY
Vx VY
VDD
C x CY
10: Circuit Families

CMOS VLSI Design 4th Ed.

27