By: Shilpi Lavania

M.Tech (VLSI Design)

CONTENTS
Introduction
What is chip and package co-design
What are clocked networks

Basic need for chip and package co-design

Important terms and terminologies
Clock Distribution
Flip chip and area I/O technology
Advantage assigning of global clock tree to package layer

Chip and Package co-design

Routing global clock on package
Case Study
Conclusion

design
ANS

What are the clocked

networks?

A clock network or clock system is a set of clocks designed to

always show exactly the same time by communicating with each

other. Clock networks usually include a central master clock kept in
sync with an official time source, and one or more slave clocks
which receive and display the time from the master.

Need of chip and

package co-design
In the designing process of SOC devices, the chip-, package-, and

board-design teams can no longer work in isolation.

Consider a chip containing 2000 pins, where the i/o assignment

and bump assignment are taking place without considering how

the die will interface to the package.

Important terms and

terminologies
Clock distribution and distribution networks
In a synchronous digital system, the clock signal is used to define a time reference

for the movement of data within that system. The clock distribution network
distributes the clock signal(s) from a common point to all the elements that need it.

1.Tree type

2.Mesh type

3. Grid type

4.H tree type

5.x-tree type

6. Tapered H-tree

Flip Chip and area i/o

technology

Routing Global Clock on

package

The layout of the two-level clock tree in the

multichip module is shown below:

Case Study

Conclusion
Routing the global clock on the package layer would provide the
following advantage:
(a)It dramatically reduces the clock skew and the path delay of the clock

network due to the very low interconnect resistance on the package

layer.
(b) It probably reduces the capacitance of the global clock network on
the package layer Low interconnect capacitance has the benefit on
the power saving of the clock net.
(c) It compacts the chip size by removing the global clock from the chip.

The case study suggests that the chip and the package should be
designed concurrently to achieve the optimum performance for VLSI
systems.

ANY
QUESTIONS