Bus Architecture

Bus defined by
Transaction protocol
Timing and signal specification
-------- bunch of wires------------ Electrical specification
Physical /mechanical characteristics
-connectors

Generic bus structure

Address width m
Data line width n handles
Carry information between source and destination
i. e. Data and address special form of data
Handles complex commands

Control lines width c handles

Signal requests and acknowledgements

Indicates type of information to be handled
Bus signals are tri-stated.
May have multiplexed address and data lines.
Every device on the bus must be able carry full load.
Bus may include timing signal for synchronisation i.e. Clock
driven
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Time multiplexed
A single bus is shared by all for handling multiple
data transfer
Saves wires in lieu of time
The bandwidth can be increased by
Non multiplexed address and data lines
Taking separate buses for address and data.
Taking so increase the cost and complexity

Increasing data width enables multiple

word transfer in single bus cycle.
Block transfer
Enables transfer of data back to back in bus
cycle.
Only one address is sent to be at the
beginning.
The bus is no released until last data is
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transferred.

Advantage & Disadvantage of bus

structure
Advantage:
Versatility:
new devices can be added without any complexity.

Low cost:
A single set of wires can be shared in many ways.

Disadvantage:
It creates communication bottleneck
i.e. Bandwidth is limited to maximum I/Os throughput.

Max. Speed is also limited by the length of bus and

number of devices connected on the bus.
There is need to support a range of devices with
Widely varying latency.
Widely varying data transfer rates.

Parallel communication
Multiple data, control information transferred
simultaneously (1 bit per wire)
High throughput with short distance
This is done when devices are connected on same
bus or circuit board.
Bus must be kept short.
Long bus induces capacitance effects which increases
delay in transfer of data
Data misalignment may occur between wires as length
increases.

High cost and bulky

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Serial communication
Single data wire and also control and power wire
Words are transmitted one bit at a time
Higher throughput with longer distance

Less average capacitance so more bits per one time can be

achieved

Cheaper and less bulky

More complex interface logic and needs
communication protocol for data transfer

Sender need to decompose the word into bits

Receiver needs to recompose the bits into words
Control signals are often send with data which increases
protocol complexity.
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Synchronous bus
Uses clock with control lines
There exist a fixed protocol for communication
relative to clock
Advantage is that it needs a little logic for
implementation and run very fast.
Disadvantage :
Every device on the bus must run on same clock rate.
To avoid clock skew the can not be long if they are fast.

Mostly this exists between processor and

memory.

Asynchronous bus
It is clock synchronised
It can accommodate a wide range of devices
Bus may be lengthened without worrying clock
skew.
It requires a handshake protocol.

Bus protocol concept

A bus transaction consists of two parts.
Issuing commands(and address) request
Transferring the data action to be taken

Master is one who starts the transaction by

issuing commands.
Slave is one who responds to the command by
Sending data to master if master asks for data
Receiving data from master if the master wants
to send data.

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Bus arbitration
Important issue in bus design is
How is the bus reserved by a device that wishes to use
it?

Master- slave arrangement

Only master has the control to access the bus i.e. It
initiates and control the bus
A slave responds to read and write requests

The simplest is that

Processor is only master
All bus must be controlled by processor only
Major drawback is that processor is involved in every
transactions.
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Bus transaction protocol without

handshaking
Master gives a request signal
enq to slave for receiving
data
Servant puts data on the line
within a time texcess

Master

en
q

dat
a

Servan
t

en
q

Master then receives the data dat

and releases the request a
signal.
Servant is then ready for next
request.
This is feasible only when all
device connected to the bus
guarantee that all the data
transfer must occur within a
bound time texcess.

texces
s

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Bus transaction protocol with handshaking

Master raises its output to signal

Master
an enquiry, which tells servant
that it should get ready to listen
for data.
When servant is ready to
receive, it raises its output to
signal an acknowledgment.
enq
At this point, master and servant
can transmit or receive.
Once the data transfer is
Ack
complete, servant lowers its
output, signalling that it has
received the data.
data
After seeing that ack has
been released, master
lowers its output.

enq
Ack
data

Servant

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Bus arbitration
Bus arbitration usually balances two factors:
Bus priority- highest priority device should be served first
Fairness- even lowest priority device should never be
completely locked out.

Bus arbitration is divided into 4 categories

Daisy chain arbitration
Parallel arbitration
Distributed arbitration by self selection-each device
waiting for the bus places a code indicating its
identity on the bus
Distributed arbitration by collision detection : each
device just go for it and problem found after fact.
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The daisy chain

Centralized bus arbitration process.
Bus control passes from one bus master to the
next one, then to the next and so on.
Devic
Devic
e1
e2
Highe
st
Grant Priorit Grant
Grant
Release
Bus
y
Arbiter
Request

Device
N
Lowest
Priority

Advantage: simple
Disadvantages:
Cannot assure fairness:
A low-priority device may be locked out indefinitely
The use of the daisy chain grant signal also limits the bus speed
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Priority based arbiter

Types of priority
Fixed priority
Each peripheral has unique rank
Highest rank chosen first with simultaneous
request
Preferred when clear difference in rank between
peripheral is done

Rotating priority (round robin)

Priority changed based on history of servicing
Better distribution of services among different
peripherals with similar demands
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Simple Implementation of a
Bus Arbiter

ReqB
ReqC

3-bit D Register

ReqA

G0

P0
Priority
P1
SetGrB
G1
ReqB
P2
EN

Clk

SetGrA
ReqA

G2

Clk

Clk

SetGrC
ReqC
Clk

J
Q
K

GrantA

J
Q
K

GrantB

J
Q
K

GrantC

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