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to VLSI Design
INTEGRATED CIRCUIT
Brief History
The First Computer: Babbage Difference Engine
(1832)
Executed basic
operations (add, sub,
mult, div) in arbitrary
sequences
Operated in two-cycle
sequence, Store, and
Mill (execute)
Included features like
pipelining to make it
faster.
Complexity: 25,000
parts.
Early Integration
Early Integration
In mid 1959, Noyce develops
the first true IC using planar
transistors, back-to-back pn
junctions for isolation, diodeisolated silicon resistors and
SiO2 insulation with evaporated
metal wiring on top
Exponential Growth
1972: 8088 introduced. Had
3,500 transistors supporting a
byte-wide data path.
Today
Many disciplines have contributed to the current state
of the art in VLSI Design:
Solid State Physics
Materials Science
Lithography and fab
Device modeling
To come up with chips like:
Intel Pentium
~3.5M
transistors
Pentium Pro
Actually a MCM comprising
of microprocessor and L2
cache
Sun UltraSparc
Pentium 4
Pentium 4
0.13-micron
process technology
(2.53, 2.2, 2 GHz)
Introduction date: January 7, 2002
Level Two cache: 512 KB Advanced
Transistors: 55 Million
Intels McKinley
Evolution of Electronics
Moores Law
IIn
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1974
1973
1972
1971
1970
1969
1968
1967
1966
1965
1964
1963
1962
1961
1960
1959
Moores Law
Evolution in Complexity
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i386
80286
100
10
i486
Pentium III
Pentium II
Pentium Pro
Pentium
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
EE414 VLSI Design
Courtesy, Intel
Moores law in
Microprocessors
Transistors (MT)
1000
100
10
486
1
386
286
0.1
0.01
P6
Pentium proc
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
Courtesy, Intel
100
10
8080
8008
4004
8086
8085
286
386
P6
Pentium
proc
486
1
1970
1980
1990
Year
2000
2010
Courtesy, Intel
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
10
8085
1
0.1
1970
8086 286
386
486
P6
Pentium proc
8080
8008
4004
1980
1990
Year
2000
2010
Courtesy, Intel
Power Dissipation
Power (Watts)
100
P6
Pentium proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Courtesy, Intel
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium proc
100
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Courtesy, Intel
Power density
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Courtesy, Intel
Power
RF
Power
Management
Analog
Baseband
Digital Baseband
(DSP + MCU)
Microscopic Problems
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.
Everything Looks a Little Different
Macroscopic Issues
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.
and Theres a Lot of Them!
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
Complexity
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Why Scaling?
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
EE414 VLSI Design
D
n+
Design Metrics
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
Die Cost
Single die
Wafer
Going up to 12 (30cm
From http://www.amd.com
-per-transistor
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
Yield
No. of good chips per wafer
Y
100%
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
die area
2 die area
Defects
is approximately 3
die cost f (die area)4
EE414 VLSI Design
Metal Line
layers width
Wafer
cost
Die
cost
386DX
0.90
$900
1.0
43
360
71%
$4
486 DX2
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
0.70
$1700
1.6
256
48
13%
$272
Pentium
0.80
$1500
1.5
296
40
9%
$417
Reliability
Noise in Digital Integrated Circuits
v(t)
VDD
i(t)
DC Operation
Voltage Transfer Characteristic
V(y)
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
OH
V(y)=V(x)
VM Switching Threshold
VOL
VOL
OH
V(x)
"1"
OH
V
IH
V(y)
Slope = -1
V
OH
Undefined
Region
"0"
V
IL
V
OL
Slope = -1
VOL
V
IL
IH
V(x)
OH
NMH
IH
Undefined
Region
V
OL
NML
IL
"0"
Gate Output
Gate Input
Noise Budget
Allocates gross noise margin to
expected sources of noise
Sources: supply noise, cross talk,
interference, offset
Differentiate between fixed and
proportional noise sources
Regenerative Property
out
v3
out
finv (v)
f(v)
v1
v1
v3
finv(v)
v2
v0
Regenerative
EE414 VLSI Design
in
f(v)
v0
v2
in
Non-Regenerative
Regenerative Property
v0
v1
v2
v3
v4
v5
V (Volt)
5
v0
v1
6
t (nsec)
v2
10
v6
M
N
(b) Fan-in M
Ri =
Ro = 0
g=
Fanout =
Vin
An Old-time Inverter
5.0
V ou t (V)
4.0
NML
3.0
2.0
VM
1.0
0.0
1.0
2.0
NMH
3.0
Vi n (V)
4.0
5.0
Delay Definitions
Vin
50%
t
Vout
tpHL
tpLH
90%
50%
10%
tf
EE414 VLSI Design
tr
Ring Oscillator
v
T = 2 tp N
EE414 VLSI Design
A First-Order RC Network
R
vin
vout
C
tp = ln (2) = 0.69 RC
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t T
1 t T
Pave
p (t )dt
isupply t dt
t
T t
T
EE414 VLSI Design
A First-Order RC Network
Vdd
E0>1=C LVdd2
A1
AN
vin
R PMOS
NETWORKvout
NMOS CL
isupply
Vout
CL
NETWORK
Vdd
T
T
E 0 1 = P t dt = V dd i sup ply t dt = Vdd CL dV out = C L V dd 2
0
0
0
T
T
Vdd
1
2
E ca p = P cap t dt = V out i ca p t dt = C L Vout dVout = C V dd
2 L
0
0
0
EE414 VLSI Design
Summary