HARDWARE

ACCELERATORS

How to improve the

performance
of a microprocessor system?

Choose a faster version of your

microprocessor
Add additional computational units
that
perform special functions?
Standard Component (Graphics
Processor)
Coprocessor (Floating-Point Processor)
Additional Microprocessor
Hardware Accelerator

Hardware Accelerators
The

hardware that performs the

acceleration, when in a separate unit from
the CPU, is referred to as ahardware
accelerator.
Works together with the processor
Executes key functions much faster than the
processor
Offloads performance critical or timecritical functions from processors.
Hardware acceleration- use of computer
hardware to perform some functions faster .

Design of a hardware accelerator

Which functions shall be implemented in

hardware and which functions in
software?
Hardware/software co-design: joint design
of hardware and software architectures
The hardware accelerator can be
implemented in

Application-specific integrated circuit.

Field-programmable gate array (FPGA).

Why accelerators?
Better performance.
Custom logic may be able to perform operation
faster than a CPU of equivalent cost.
CPU cost is a non-linear function of performance.
To improve performance by choosing a faster
CPU may be very expensive!
Good for processing I/O in real-time.
May consume less energy.
May be better at streaming data.

HARDWARE ACCELERATORS BOOST

PERFORMANCE OF SHARC PROCESSORS

Analog Devices SHARC ADSP-2146x

Processor
Hardware accelerators in the processor
implements:

FIR (finite impulse response),

IIR (infinite impulse response), and
FFT (fast fourier transform).

Why hardware accelerators

needed here?
Dedicated

fixed-function peripherals
Perform a single computationally intensive
task over and over.
Offloads the main processor
Cost-effective way to increase
computational power of processor
Example: audio systems, where the number
of channels is on the rise.

Accelerators in SHARC ADSP2146x

Features-rich core and peripherals
Higher clock speed (450 MHz) and expanded onchip memory (5 Mb).
Features a set of hardware accelerators for
implementing
FIR filters
IIR filters and FFTs.

Accelerators complement the on-board sample rate

converter, which was introduced in the
SHARC ADSP-2136x processor

Hardware accelerator
architecture
All

three accelerators for the SHARC ADSP2146x have a similar design.

FIR ACCELERATOR has the following
components:

Set of control registers

DMA controller
Two blocks of local memory
Compute unit has four parallel MACs.

accelerator
architecture

FIR ACCELERATOR

The FIR accelerator typically progresses through the

following steps:
1. Load the coefficient data for this channel from internal
memory to the local accelerator coefficient storage.
2. Load the state variables for this channel from internal
memory to the local accelerator state variable storage.
3. Compute the output sample using the four MAC units.
4. Store the result.
5. If there are samples left to process, then fetch the next
input sample and write to the state variable storage.
6. Repeat steps 3 to 5 until all the output samples in the
channel are computed.
7. Repeat steps 1 to 6 for all input channels.

The ADSP-2146x core

maximum clock rate 450 MHz.
using SIMD , it performs two MAC operations per
clock cycle for a peak rate of 900 MMAC/sec.

The accelerator
Operates at the SHARC peripheral clock rate of
225 MHz.
Uses four dedicated MAC units
Achieves peak rate of 900MMAC/sec.

 Total

number of peripheral clock cycles

needed to implement a given FIR filter is
given by the formula

where N is the number of filter taps and B

is the block size.

Conclusion
The hardware accelerators in SHARC ADSP2146x processor provide a significant boost
in overall processing power.
Offload common signal processing
operations from the core processor.
This doubles the computational throughput
of the processor.

THANK YOU