IC LAYOUT ENGINEERING

Introduction to VLSI &ASIC

DESIGN
DAY ~ 2

EVOLUTION OF
ELECTRONICS
YEAR

ERA

TECHNOLOGICAL
BREAKTHROUGH

1920 -- Vacuum Tube - Vacuum Technology -- Glass to metal seal

1948 -- Transistor fabrication

-- Crystal growth

1958 -- SSI - Planar technology - Digital Gates -- Photolithography

1962 -- MSI - PMOS Technology - Registers,
decoders, muxes
1968 -- LSI - NMOS Technology- Memory

-- Gate Oxide

1978 -- VLSI - CMOS Technology

Micro processors

-- multi layer interconnect

Technology

-- ION Implantation & CVD

MOORES
LAW
In 1969, Gorden Moore stated that Silicon
Technology will double the number of transistors
per chip every 18 months!!!
And it is happening!!!!!!!
Now Moores law has become self sustaning

INTEGRATION
LEVEL
Types of integration

gates per chip

SSI small-scale integration

~10
60s
MSI medium-scale integration
~1001000 70s
LSI large-scale integration
~100010,000 80s
VLSI very large-scale integration 10,000100,000 90s
ULSI ultra large scale integration ~1M10M

ADVANTAGES OF
VLSI
REDUCTION IN

INCREASE IN

Design cycle time

Speed

Product Size

Design Security

Power Consumption

Productivity

Cost

Design Flexibility

THE GOAL OF ASIC

DESIGNER
Meet the market requirement
Satisfying the customer need
Beating the competition
Increasing the functionality
Reducing the cost
Achieved by
Using the next generation Silicon Technologies
New Design concept and Tools
High Level Integration

VLSI
TECHNOLOGY

Backbone for all IT advancements.

A Technology solution and not a product.
Packages lot of circuitry ( Millions of Gates]
Miniaturisation
Confidentiality
Low power operation

Hand held battery operated gadgets

APPLICATIO
NS
High Performance computing
Datacom/ Networking
Telecom/MOBILE/CELL/ WIL
Multimedia
Smart Cards
Remote Controls

THE PERFORMANCE CUBE

Delay

Power
Cost

Smaller is Better

Over View
Of
VLSI DESIGN METHODOLOGY

VLSI OVERVIEW
Customer

Specification

VLSI
TECHNOLOGY
Full
Custom
ASIC

Semi -Custom
ASIC

Gate Array
ASIC

FPGA
ASIC

VLSI OVERVIEW(cont)
Customer

Gate Level
Net List

Specification

Logic Design/
Front End

FPGA
ASIC
Full Custom
ASIC

Semi -Custom
ASIC

Gate Array
ASIC

VLSI OVERVIEW
Customer

Gate Level
Net List
Physical
layout

Specification

Logic Design/
Front End
Physical Design/
Back End

Full
Custom
ASIC

Semi -Custom
ASIC

Gate Array
ASIC

FPGA
ASIC

VLSI
TECHNOLOGY
Encompasses 3 Technologies.
Electronic Design
At the Code
Physical design
As means Layout
Fabrication
As means final product

LOGIC
DESIGN

Blocking assignment

always @(A1 or B1 or C1 or M1)

// blocking assignments

begin: BLOCK_COMB
M1 = #3 (A1 & B1);
Y1 = #1 (M1 | C1);
end

A1
B1
C1
M1
Y1

behavioral

13

PHYSICAL
DESIGN

Masks

FOUNDR
Y
Processed
Wafer

Si wafer
ASIC
processing

Chips

Chemicals

Finished
ASIC

DESIGN METHODOLOGIESCHART
BEHAVIORAL DOMAIN

Synthesis

STRUCTURAL DOMAIN

Application algorithms

processors

programs
Subroutines ,B.equations
instructions

ALUs , registers
Logic gates
Transistors

Layout transistor

Logic abstraction level

Cells
Chips / modules

Circuit abstraction level

Chips.MCM,boards
Physical domain

System abstractio
level
Micro architecture
abstraction level

Overview Of VLSI Design Methodology

Summary

DAY ~ 2

Thank You