ECE 301 Digital Electronics

Flip-Flops and Registers

(Lecture #15)

Basic Memory Elements

ECE 301 - Digital Electronics

Basic Memory Elements

Basic Latch

A feedback connection of two NOR gates or two

NAND gates, which can store one bit of information.

Gated Latch

Can be set to 1 or reset to 0.

A basic latch that also includes input gating and a

control input signal (i.e. the clock).

Flip-Flop

A storage element based on the gated latch principle,

which can have its output state changed only on the
edge of the controlling clock signal.
ECE 301 - Digital Electronics

D Flip-Flop

ECE 301 - Digital Electronics

D Flip-Flop

Master-Slave Flip-Flop

ECE 301 - Digital Electronics

D Flip-Flop: Master-Slave

ECE 301 - Digital Electronics

D Flip-Flop

Positive Edge-triggered Flip-Flop

ECE 301 - Digital Electronics

D Flip-Flop: Symbols

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D Flip-Flop: Function Table

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Basic Memory Elements

Comparison of
Level-Sensitive and Edge-Triggered
Memory Elements

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D
Clock

Note that the Latch,

Positive Edge-triggered FF,
and Negative Edge-triggered FF
each have a unique symbol

Qa

Clk Q

Qa

Qb

Qb

Qc

Qc

Gated D Latch

Positive Edge-triggered
D Flip-Flop

Negative Edge-triggered
D Flip-Flop

(a) Circuit
Clock
D
Qa

Gated D Latch

Qb

+ Edge-triggered D FF

Qc

- Edge-triggered D FF

(b) Timing diagram

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Flip-Flops

Asynchronous Preset and Clear Signals

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Asynchronous Preset and Clear

Preset
D

Clock

Clear
(a) Circuit

master

slave

Preset
D

Q
Q

Clear
(b) Graphical symbol

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Flip-Flops

JK Flip-Flop

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JK Flip-Flop

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JK Flip-Flop

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Flip-Flops

T Flip-Flop

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T Flip-Flop

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T Flip-Flop

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Registers

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Registers

Register

Consists of N Flip-Flops

Stores N bits

Common clock used for all Flip-Flops

Shift Register

A register that provides the ability to shift its

contents (either left or right).

Must use Flip-Flops

Either edge-triggered or master-slave

Cannot use Level-sensitive Gated Latches

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Registers

4-bit Register

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ECE 301 - Digital Electronics

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Registers

4-bit Register with Parallel Load

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2-to-1 Multiplexer
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Registers

4-bit Serial-In Serial-Out

Shift Register

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4-bit SI/SO Shift Register

common clock

Edge-triggered
Flip-Flop

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Registers

Parallel-In Parallel-Out
Shift Register

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Registers

Parallel-In Parallel-Out
Bi-directional Shift Register

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4-bit PI/PO Bi-directional

Shift Register

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Acknowledgments

The slides used in this lecture were taken, with permission,

from those provided by Pearson Prentice Hall for
Digital Design (4th Edition).
They are the property of and are copyrighted by
Pearson Education.

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