Pin Configuration of 8086

8086 is 40 pin IC
HMOS technology
Approximately 29,000 transistors
Available in 3 clock frequencies
5 MHz, 8 MHz, 10 MHz

Modes of operation
Minimum mode
Small systems
Single processor
Bus control signals generated by the processor

Maximum mode
Medium to large systems
Two or more processors
External bus controller is used to generate bus control

signals

Pin Diagram
Some

pins have common

functions in both the modes
Pin

numbers 24-31 have

different functions in minimum
and maximum mode
Pin 33 determines the mode
Connected to ground

Maximum mode
Connected to
Minimum mode

+5

V-

Pins common to Min/Max mode

Pin
numbers

Symbol

In/Out

Description

1 and 20

GND

Pins are grounded

40

VCC

Supply voltage
+5 V 10%

19

CLK

Clock input
33% duty cycle
Clock frequency depends on CPU
model

33

MN/ MX

+5 V Minimum mode
Ground Maximum mode

Pin
numbers

Symbol

In/Out

Description

17

NMI

Non-maskable interrupt
Positive-edge triggered

18

INTR

Maskable interrupt
Level triggered
Active high

21

RESET

Active high
Must be active for at least four
clock cycles
Terminates current activity
Clears-PSW, IP, DS, ES, SS, IQ
SET- CS to FFFF

22

READY

Active high
Acknowledgement from slow
devices

Examined by WAIT instruction

1-idle state ; 0-continue
processing

23

TEST

Pin
Symbol
numbers
32

RD

In/
Ou
t
O

Description

0-Read operation

39, 2-16

AD15, AD14AD0

I/O

Multiplexed address bus (A15-A0)

and data bus (D15-D0)

35-38

A19/S6-A16/S3

Multiplexed address (A19-A16) and

status lines (S6-S3)
S6-0
S5-current setting of IF
S 4 S3 Segment Register
0
0
ES
0
1
SS
1
0
CS or none
1
1
DS

Pin
Symbol
numbers
34

BHE / S7

In/
Ou
t
O

Description

BHE

Multiplexed Bus High Enable

and Status line (S7)
S7-1

Operation
Write/ read a word
at an even address
Write/ read a byte
at an even address
Write/ read a byte
at an odd address
Write/ read a word
at an odd address

BHE

A0

Data pins used

D15 - D 0 (One bus cycle)

D 7 - D 0 (One bus cycle)

D15 - D8 (One bus cycle)

D15 - D8 (First bus cycle :

Least significant byte on D15 - D8)
D 7 - D 0 (Next bus cycle :
Most significant byte on D 7 - D 0)

Pins for Minimum Mode

Pin
numbers
24

25

26

Symbol

INTA

ALE

DEN

In/Out

Description

Interrupt acknowledgement for

INTR
Indicates recognition of interrupt
request

Outputs a pulse at the beginning of

the bus cycle
Indicates availability of valid
address

Output during later part of the bus

cycle
Informs the transceivers that CPU
is ready to send or receive the data

Pins for Minimum Mode

Pin
numbers

Symbol

In/Out

Description

27

DT/ R

Indicates transceivers to transmit or

receive data
1-transmit
0-receive

28

M/ IO

Distinguishes memory transfer from

I/O transfer
1-memory
0-I/O

0-write operation

29

WR

Pins 28, 29, 32 indicate the type of transfer

M/ IO
0
0
1
1

RD
0
1
0
1

WR
1
0
1
0

I/ O Read
I/ O Write
Memory Read
Memory Write

Pins for Minimum Mode

Pin
numbers

Symbol

In/Out

Description

31

HOLD

1-another master is requesting the

bus access
NO control of the bus until this
signal goes low

30

HLDA

Hold acknowledgement signal

Following pins are put in high
impedance state
AD0-AD19
BHE / S7, RD, WR, M/ IO
DEN, DT/ R, INTA

Minimum Mode System

Application of 8282 latches

8282 : 20 pin IC, 8 bit latch
Latching accomplished using 3 Intel-8282
20-bit address ready to be latched
ALE (Address Latch Enable)

8282s STB is connected to 8086s ALE

Active low OE is grounded to enable the latches
IC 74LS373 another commonly used octal latch

Application of 8286 transceivers

OE 1, transceiver is

When

disabled
When OE 0,
T=1, transmitter
T=0, receiver
8286s

OE 0 connected with

8086s DEN
8286s T connected with 8086s

DT/ R
2- 8286 are connected
20 pin IC
Increase current sourcing/sinking

capacity

8284A clock generator

18-pin IC
External oscillator connected

across X1 and X2
EFI is connected to external
clock frequency input
CLK is one-third of the input
frequency
When F/ C 1, EFI
determines the frequency
When F/ C 0, oscillator
input determines the
frequency
Main functions
CLK generation
RESET synchronization

Bus Cycle
Bus

cycle

time

required

for

single

read/write

microprocessor and external memory(or I/O)

T-state one cycle of the clock
Read cycle
Transfer data from Memory (I/O) to processor
Write cycle
Transfer data from processor to Memory (I/O)

Length of bus cycle - 4 clock cycles (T 1,T2,T3,T4)

If Bus inactive between two Bus cycles
Idle state clock cycles (T I)
When READY is zero, Tw inserted between T3 and T4

operation

between

Read Cycle

Write Cycle

Pins for Maximum Mode

Pin
Symbol
numbers

In/Out

Description

24,25

Reflects the status of the instruction

queue

QS1,QS0

QS1 QS0
0

No instruction was taken

from the queue
First byte of current instruction
was taken from the queue
Queue was flushed because
of a transfer instruction
A byte other than the first byte
was taken from the queue

Pins for Maximum Mode

Pin
Symbol
numbers

In/Out

Description

26,27,28

Indicates the type of transfer

during current bus cycle

S0, S1, S2

S2 S1 S0
0 0 0 Interrupt acknowledge
0 0 1
Read I/ O port
0 1 0
Write I/ O port
0 1 1
Halt
1 0 0
Instruction fetch
1 0 1
Read memory
1 1 0
Write memory
1 1 1
Inactive

Pins for Maximum Mode

Pin
numbers
29

30

31

Symbol

LOCK

RQ GT1

RQ GT 0

In/Out

Description

Indicates that bus is not to be

relinquished to other potential
masters
Initiated by LOCK instruction prefix
Maintained until end of the next
instruction

I/O

For inputting bus requests and

outputting bus grants

I/O

Same as RQ GT1, but has higher

priority

Maximum Mode System

Read cycle

Write cycle