DIGITAL COUNTERS

GROUP MEMBERS
MTHOKOZISI MAHONONDO (R167059A)
BORNWELL KANDIERO (R167445V)
ERIC MWALE (R167719B)
NGONIDZASHE MATAVIRE (R169030J)
TAPIWANASHE MUGONIWA (R169546Y)

DEFINITION
These are the fundamental components of digital
systems. They can be used intiming (sampling signals)
as well as control and sequencing applications.
In digital logic and computing ,a counter is a device
which stores (or sometimes displays) the number of
times a particular event or process has occurred, often
in relationship to a clock signal.

TYPICAL APPLICATIONS
These include among others:
Special counter - also called program counter and is used within microprocessors

and contain the address of the next instruction to be executed by the

microprocessor;
Direct counting this might be necessary to count manufactured objects on a
conveyer belt;
Time and frequency measurements counters are used to measure time
needed or taken either during processing or during transmission of data or
information
Analogue to digital conversion counters are also used during converting data
from analogue form to digital form and vice-versa.

MODES OF DIGITAL COUNTERS

Digital counter is a circuit capable of counting the number of
pulses applied to one of its inputs. Essentially, a counter consists
of a number of flip-flops connected in series. Typically counters are
built using the JK or D flip-flops. When using a flip flop as part of a
counter it must be capable of changing its output state at each
clock pulse (toggling). The JK flip flop is good at this operation.
Counters operate in two modes, namely: Asynchronous and
Synchronous.

Asynchronous Counter - have no common control, which means a

change in one section of the system causes further changes in other
sections and so on.

Synchronous Counter - all outputs are directly clocked at the same

time by the input clock signal.

ASYNCHRONOUS 4 BIT BINARY

UP COUNTER

 The 4-bit asynchronous counter above is constructed from four

master slave J K flip-flops. The Q output from each flip-flop is
connected to the clock input of the next flip flop in the chain. With
all J-K inputs connected to a +5v via a resistor (1kilo Ohm), they are
held at a HIGH level(binary 1), which ensures that each flip flop is
capable of toggling. In this mode the flip-flops are sometimes known
as T (for toggle) flip-flops.The outputs of the four flip-flops are being
monitored by Light Emitting Diodes (LEDs), D1 to D4. Resistors R2
to R5 are current limiting resistors (220 Ohms would be
enough).Before the count begins all flip-flops are CLEARED, that is
all Q outputs = 0.Because master slave devices are used whenever
the signal clock input changes from 1 to 0, the flip-flop will toggle.

 FF0 will toggle as each input pulse goes from 1 to

0.For 16 input pulses it will produce 8 output
pulses at Qo. The output of the second flip-flop
(FF1) will change whenever Qo output goes from
High to LOW ( 1 to 0).For eight (8) input pulses to
FF1, it will produce 4 pulses at its output Q1. The
four Pulses at Q1 output are used to clock FF2.
FF2 therefore produces two output pulses which
are used to clock FF3. The output from FF3 is a
single pulse. Because each stage must wait for a
change in the previous one before it can begin to
change, the circuit is therefore asynchronous.

AN ASYNCHRONOUS 4-BIT BINARY UP

COUNTER TIMING DIAGRAM

AN ASYNCHRONOUS 4-BIT
DOWN COUNTER

 In Up Counters each flip flop is triggered by the Q output of the

preceding stage. In a down counter each flip-flop is triggered by the
output (not Q) of the preceding flip flop. In both counters the first flip-flop
is triggered by the clock. Assume that each flip-flop is triggered as the
clock changes from 1 to 0 and they are all initially set to 1. The output
(Q0) from the first flip-flop (FF0) changes state whenever the input pulses
change from 1 to 0. FF1 is triggered by (the inverse of Q), therefore it
will change state when Q will be going from 0 to 1( will be going from 1
to 0). Flip flops FF2 and FF3 operate in a similar manner.

SYNCHRONOUS COUNTERS
These were developed to overcome the disadvantages of asynchronous
counters.
Among the many advantages of synchronous counters include simplicity
and also that they require fewer components to produce a given counting
sequence.
The major disadvantage of asynchronous counters is caused by their
basic principle of operation, that is each flip- flop is triggered by the
transition at the output of the preceding flip flop. Because of the inherent
propagation delay time, p.d.t, of each flip-flop, this means that the
second flip flop will not respond until a time equal to 2 x p.d.t after the
clock pulse occurs and so on.

 In other words it means that the Nth flip flop will not respond until after a
time equal to N x p.d.t after the clock pulse occurs.
Because each input pulse essentially ripples through all of the flip-flops
in the counter, the time taken for one pulse to ripple through the
counter with a large number of flip-flops may be greater than the arrival
of the next input pulse to the counter, and as a result false counts may
occur.
The accumulative effect of the flip flop delays is to limit the speed of
operation of asynchronous counters. So these limitations can be
overcome with the use of synchronous counters in which all of the flip
flops are triggered by the same clock input pulse.

EXAMPLE OF A 4-BIT
SYNCHRONOUS BINARY
COUNTER

The 4-Bit Synchronous Binary Up Counter works as follows:

The counter is initially cleared by applying a LOW pulse at the CLEAR (CLR) input.
FF0 which has J-K inputs permanently tied to a HIGH level will toggle from 1 to 0
when the first pulse is applied. Since the J-K inputs of are now HIGH, the next
clock pulse will change Q1 to 1 and Q0 back to 0 to give an out count of 0010 2 or
210 With Q0 now LOW, only Q0 can now change on the next clock pulse and this
gives an output of 00112 or 310. Since Q0 and Q1 are now both HIGH, gate G1 will
be HIGH and put a HIGH on J and K input of FF2 so that on the next clock pulse Q2
will become a 1(HIGH) while Q0 and Q1 will change to 0(LOW), giving an output of
01002or 410. The rest of the count sequence follows a similar pattern. At the count
of 7 when Q0, Q1 and Q2 all HIGH (1s) AND gate G2 will enable FF3 to toggle to 1
giving a count of 8. At count 15 all of the outputs are HIGH, so they toggle back to
0 on the next clock pulse.

A SYNCHRONOUS 4-BIT BINARY UP

COUNTER TIMING DIAGRAM