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Overview
What is PLD??
Why Programmable logic?
Programmable logic technologies
Read-Only Memory (ROM)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
CPLD and FPGA
Programmable
Devices (PLD)
Logic
Programmable
Devices (PLD)
Logic
Programmable
Devices (PLD)
Logic
General structure of
PLDs.
Buffer/inverter
(a) Symbol.
Programming by blowing
fuses.
OR - PLD Notation
Why Programmable
Logic?
Facts:
It is most economical to produce an IC in large
volumes
Many designs required only small volumes of ICs
Programmable
Configurations
Read Only Memory (ROM) - a fixed array of AND
gates and a programmable array of OR gates
Programmable
Array
Logic
(PAL)
a
programmable array of AND gates feeding a fixed
array of OR gates.
Programmable
Logic
Array
(PLA)
programmable array of AND gates feeding
programmable array of OR gates.
a
a
Fixed
AND array
(decoder)
Programmable
Connections
Programmable
OR array
Outputs
Programmable
Connections
Inputs
Programmable
AND array
Fixed
OR array
Outputs
Inputs
Outputs
A
B
C
D7
D6
D5
D4
A2 D3
D2
A1 D1
A0 D0
X
X
F3
F2
F1
F0
Read Example:
For input (A2,A1,A0) = 011, output is (F3,F2,F1,F0 ) = 0011.
Disadvantage
ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N
and M
Some PALs have outputs that can be complemented,
adding POS functions
No multilevel circuit implementations in ROM (without
external connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits
easier.
Programmable Programmable
Fixed
Inputs
Outputs
Connections
AND array
OR array
x1 x2
xn
Input buffers
and
inverters
x1 x1
fixed connections
xn xn
P1
AND plane
Pk
OR plane
f1
fm
PAL Logic
Design Example: BCD to Gray Code Converter
Implementation
Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
AB
00
CD
01
11
10
AB
00
CD
A
01
11
10
00
00
01
01
11
11
10
10
D
C
D
C
B
K-map for W
AB
00
CD
B
K-map for X
A
01
11
10
00
01
AB
00
CD
A
01
11
10
00
01
11
10
Minimized Functions:
W =A+ B D + B C
X=BC
Y=B+C
Z =AB C D + B C D +AD + B C D
K-maps
11
C
10
B
K-map for Y
B
K-map for Z
PAL Logic
Implementation
A B
C D
A
BD
BC
Minimized Functions:
0
BC
W =A+ B D + B C
X=BC
Y=B+C
Z =AB C D + B C D +AD + B C D
0
0
0
B
C
0
0
ABCD
BCD
AD
BCD
22
Advantages
A PLA can have large N and M permitting implementation of
equations that are impractical for a ROM (because of the
number of inputs, N, required
A PLA has all of its product terms connectable to all outputs,
overcoming the problem of the limited inputs to the PAL Ors
Some PLAs have outputs that can be complemented, adding
POS functions
Disadvantage
Often, the product term count limits the application of a PLA.
Two-level multiple-output optimization reduces the number
of product terms in an implementation, helping to fit it into a
PLA.
Programmable Programmable Programmable Programmable
AND array
OR array
Connections
Connections
Inputs
Outputs
x1 x2
The connections in
the AND plane are
programmable
Input buffers
and
inverters
x1 x1
The connections in
the OR plane are
programmable
xn
xn xn
P1
AND plane
Pk
OR plane
f1
fm
x2
x3
Programmable
connections
f1 = x1x2+x1x3'+x1'x2'x3
P1
OR plane
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4
AND plane
f1
f2
x2
x3
OR plane
f1 = x1x2+x1x3'+x1'x2'x3
P1
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4
AND plane
f1
f2
A
01
11
10
00
01
AB
00
CD
A
01
11
10
ABCD
ABCD
00
01
ABCD
D
11
11
ABCD
10
AC
C
10
AB
00
CD
00
01
AC
K-map for EQ
K-map for NE
BD
BD
AB
00
CD
01
11
10
00
01
01
11
10
D
11
BCD
ABC
ABD
11
10
BCD
C
10
B
K-map for LT
B
K-map for GT
EQ
NE
LT
GT
27
28
29
FPGA Structure
Typical organization in 2-D array
Configurable logic blocks (CLBs) contain
functional logic
Combinational functions plus FFs
Complexity varies by device
30
FPGA Structure
Input/Output
Block
IOB
IOB
IOB
CLB
CLB
CLB
CLB
SM
IOB
SM
CLB
SM
IOB
Configurable
Logic
Block
CLB
CLB
CLB
CLB
IOB
SM
SM
IOB
CLB
Switch
Matrix
IOB
IOB
CLB
SM
IOB
IOB
IOB
SM
CLB
SM
SM
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
Chapter 3 - Part 2
32
Summary
What is PLD??
Why programmable logic?
Programmable logic technologies
Read-Only Memory (ROM)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)