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Chapter 9

Programmable Logic Devices


(PLD)

Overview
What is PLD??
Why Programmable logic?
Programmable logic technologies
Read-Only Memory (ROM)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
CPLD and FPGA

Programmable
Devices (PLD)

Logic

Problems by Using Basic Gates


Many components on PCB:
As no. of components rise, nodes interconnection
complexity grow exponentially.
Growth in interconnection will cause increase in
interference, PCB size, PCB design cost, and
manufacturing time

Programmable
Devices (PLD)

Logic

The purpose of a PLD device is to permit elaborate digital logic designs


to be implemented by the user in a single device.
Can be erased electrically and reprogrammed with a new design, making
them very well suited for academic and prototyping
Types of Programmable Logic Devices
SPLDs (Simple Programmable Logic Devices)

ROM (Read-Only Memory)


PLA (Programmable Logic Array)
PAL (Programmable Array Logic)
GAL (Generic Array Logic)

CPLD (Complex Programmable Logic Device)


FPGA (Field-Programmable Gate Array)

Programmable
Devices (PLD)

Logic

The first three varieties are quite similar to each


other:
They all have an input connection matrix, which
connects the inputs of the device to an array of ANDgates.
They all have an output connection matrix, which
connect the outputs of the AND-gates to the inputs of
OR-gates which drive the outputs of the device.

The gate array is significantly different and will be


described later.

Programmable Logic Devices (PLD)


The differences between the first three categories are these:
1. In a ROM, the input connection matrix is hardwired. The
user can modify the output connection matrix.
2. In a PAL/GAL the output connection matrix is hardwired.
The user can modify the input connection matrix.
3. In a PLA the user can modify both the input connection
matrix and the output connection matrix.

General structure of
PLDs.

Buffer/inverter

(a) Symbol.

(b) Logic equivalent.

Programming by blowing
fuses.

(a) Before programming.

(b) After programming.

OR - PLD Notation

AND - PLD Notation

Why Programmable
Logic?
Facts:
It is most economical to produce an IC in large
volumes
Many designs required only small volumes of ICs

Need an IC that can be:


Produced in large volumes
Handle many designs required in small volumes

A programmable logic part can be:


made in large volumes
programmed to implement large numbers of
different low-volume designs

Programmable Logic - Additional


Advantages
Many programmable logic devices are fieldprogrammable, i.e., can be programmed outside of the
manufacturing environment
Most programmable logic devices are erasable and
reprogrammable.
Allows updating a device or correction of errors
Allows reuse the device for a different design - the ultimate in
re-usability!
Ideal for course laboratories

Programmable logic devices can be used to prototype


design that will be implemented for sale in regular ICs.
Complete Intel Pentium designs were actually prototype with
specialized systems based on large numbers of VLSI
programmable devices!

Programmable
Configurations
Read Only Memory (ROM) - a fixed array of AND
gates and a programmable array of OR gates
Programmable
Array
Logic
(PAL)
a
programmable array of AND gates feeding a fixed
array of OR gates.
Programmable
Logic
Array
(PLA)
programmable array of AND gates feeding
programmable array of OR gates.

PAL is a registered trademark of Lattice Semiconductor Corp.

a
a

ROM, PAL and PLA


Configurations
Inputs

Fixed
AND array
(decoder)

Programmable
Connections

Programmable
OR array

Outputs

(a) Programmable read-only memory (PROM)

Programmable
Connections

Inputs

Programmable
AND array

Fixed
OR array

Outputs

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable


AND array
OR array
Connections
Connections

Inputs

(c) Programmable logic array (PLA) device

Outputs

Read Only Memory


Read Only Memories (ROM) or Programmable Read Only Memories
(PROM) have:
N input lines,
M output lines, and
2N decoded min-terms.

Fixed AND array with 2N outputs implementing all N-literal min-terms.


Programmable OR Array with M outputs lines to form up to M sum of
min-term expressions.
A program for a ROM or PROM is simply a multiple-output truth table
If a 1 entry, a connection is made to the corresponding min-term for the
corresponding output
If a 0, no connection is made

Can be viewed as a memory with the inputs as addresses of data


(output values), hence ROM or PROM names!

Read Only Memory Example


Example: A 8 X 4 ROM (N = 3
input lines, M= 4 output lines)
The fixed "AND" array is a
decoder with 3 inputs and 8
outputs
implementing
minterms.
The
programmable
"OR
array uses a single line to
represent all inputs to an
OR gate.
An X in the
array corresponds to attaching
the min-term to the OR

A
B
C

D7
D6
D5
D4
A2 D3
D2
A1 D1
A0 D0

X
X

F3

F2

F1

F0

Read Example:
For input (A2,A1,A0) = 011, output is (F3,F2,F1,F0 ) = 0011.

What are functions F3, F2 , F1 and F0 in terms of (A2,


A1, A0)?

Programmable Array Logic


(PAL)
The PAL is the opposite of the ROM, having a
programmable set of ANDs combined with fixed ORs.

Disadvantage
ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N
and M
Some PALs have outputs that can be complemented,
adding POS functions
No multilevel circuit implementations in ROM (without
external connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits
easier.
Programmable Programmable
Fixed
Inputs
Outputs
Connections

AND array

OR array

(b) Programmable array logic (PAL) device

Programmable Array Logic


(PAL)
Also
used
to
implement
circuits in SOP form
The connections in
the AND plane are
programmable
The connections in
the OR plane are
NOT programmable

x1 x2

xn

Input buffers
and
inverters
x1 x1

fixed connections

xn xn
P1

AND plane

Pk

OR plane

f1

fm

PAL Logic
Design Example: BCD to Gray Code Converter
Implementation
Truth Table

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X

X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X

Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X

Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X

AB
00
CD

01

11

10

AB
00
CD

A
01

11

10

00

00

01

01

11

11

10

10

D
C

D
C

B
K-map for W
AB
00
CD

B
K-map for X

A
01

11

10

00

01

AB
00
CD

A
01

11

10

00

01

11

10

Minimized Functions:
W =A+ B D + B C
X=BC
Y=B+C
Z =AB C D + B C D +AD + B C D

K-maps

11

C
10

B
K-map for Y

B
K-map for Z

PAL Logic
Implementation
A B

C D
A
BD
BC

Minimized Functions:

0
BC

W =A+ B D + B C
X=BC
Y=B+C
Z =AB C D + B C D +AD + B C D

0
0
0
B
C
0
0
ABCD
BCD
AD
BCD

22

Programmable Logic Array


(PLA
)
Compared to a ROM and a PAL, a PLA is the most
flexible having a programmable set of ANDs combined
with a programmable set of ORs.

Advantages
A PLA can have large N and M permitting implementation of
equations that are impractical for a ROM (because of the
number of inputs, N, required
A PLA has all of its product terms connectable to all outputs,
overcoming the problem of the limited inputs to the PAL Ors
Some PLAs have outputs that can be complemented, adding
POS functions

Disadvantage
Often, the product term count limits the application of a PLA.
Two-level multiple-output optimization reduces the number
of product terms in an implementation, helping to fit it into a
PLA.
Programmable Programmable Programmable Programmable
AND array
OR array
Connections
Connections

Inputs

(c) Programmable logic array (PLA) device

Outputs

Programmable Logic Array


(PLA)
Use to implement
circuits in SOP form

x1 x2

The connections in
the AND plane are
programmable

Input buffers
and
inverters
x1 x1

The connections in
the OR plane are
programmable

xn

xn xn
P1

AND plane

Pk

OR plane

f1

fm

Programmable Logic Array (PLA) example


x1

x2

x3
Programmable
connections

f1 = x1x2+x1x3'+x1'x2'x3

P1

OR plane

f2 = x1x2+x1'x2'x3+x1x3
P2

P3

P4

AND plane
f1

f2

Programmable Logic Array (PLA) example


x1

x2

x3

OR plane

f1 = x1x2+x1x3'+x1'x2'x3

P1

f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4

x marks the connections left in


place after programming

AND plane
f1

f2

PLA Logic Implementation


Magnitude Comparator
AB
00
CD

A
01

11

10

00

01

AB
00
CD

A
01

11

10

ABCD
ABCD

00

01

ABCD

D
11

11

ABCD

10

AC

C
10

AB
00
CD
00
01

AC

K-map for EQ

K-map for NE

BD

BD

AB
00
CD

01

11

10

00

01

01

11

10

D
11

BCD
ABC

ABD

11

10

BCD

C
10

B
K-map for LT

B
K-map for GT

EQ

NE

LT

GT

27

Complex Programmable Logic Devices


Complex PLDs typically combine PAL
combinational logic with FFs

Organized into logic blocks


Fixed OR array size
Combinational or registered output
Some pins are inputs only

Usually enough logic for simple counters,


state machines, decoders, etc.

28

Field Programmable Gate


Arrays (FPGAs)
FPGAs have much more logic than CPLDs
2K to >10M equivalent gates
Requires different architecture
FPGAs can be RAM-based or Flash-based
RAM FPGAs must be programmed at power-on
External memory needed for programming data
May be dynamically reconfigured

Flash FPGAs store program data in non-volitile


memory
Reprogramming is more difficult

29

FPGA Structure
Typical organization in 2-D array
Configurable logic blocks (CLBs) contain
functional logic
Combinational functions plus FFs
Complexity varies by device

CLB interconnect is either local or long line


CLBs have connections to local neighbors
Horizontal and vertical channels use for long
distance
Channel intersections have switch matrix

IOBs (I/O logic Blocks) connect to pins


Usually have some additional C.L./FF in block

30

FPGA Structure
Input/Output
Block

IOB

IOB

IOB

CLB

CLB

CLB

CLB

SM

IOB

SM

CLB
SM

IOB

Configurable
Logic
Block

CLB

CLB

CLB

CLB

IOB

SM

SM

IOB

CLB

Switch
Matrix
IOB

IOB

CLB

SM

IOB

IOB

IOB

SM

CLB
SM

SM

CLB

CLB

CLB

CLB

IOB

IOB

IOB

IOB

Chapter 3 - Part 2

32

Summary
What is PLD??
Why programmable logic?
Programmable logic technologies
Read-Only Memory (ROM)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)

Examples of using programmable logic


CPLD
FPGA

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