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Real Time
Systems
Embedded
Systems
Examples
Real Time Embedded:
Characteristics of RTS
Event-driven, reactive.
High cost of failure.
Concurrency/multiprogramming.
Stand-alone/continuous operation.
Reliability/fault-tolerance requirements.
Predictable behavior.
Time
now
instant
event
instant
duration
event
past
future
time line
digital clock
tick
granule
Definitions
Real real-time systems which are hard real-time and which the
response times are very short. E.g. Missile guidance system.
A single system may have all hard, soft and real real-time subsystems.
In reality many systems will have a cost function associated with
missing each deadline
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Control systems
Man-Machine
Interface
Operator
Instrumentation
Interface
Real-Time
Computer
System
Controlled
Object
A/D
A/D
rk
yk
control-law
computation
y(t)
sensor
Outside effects
uk
D/A
u(t)
plant
actuator
The system
being controlled
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set
settimer
timerto
tointerrupt
interruptperiodically
periodicallywith
withperiod
periodT;
T;
at
ateach
eachtimer
timerinterrupt
interruptdo
do
do
doanalog-to-digital
analog-to-digitalconversion
conversionto
toget
gety;
y;
compute
computecontrol
controloutput
outputu;
u;
output
outputuuand
anddo
dodigital-to-analog
digital-to-analogconversion;
conversion;
end
enddo
do
Taxonomy of Real-Time
Systems
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Taxonomy of Real-Time
Systems
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Taxonomy of Real-Time
Systems
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Taxonomy: Static
Task arrival times can be predicted
Static (compile-time) analysis
possible
Allows good resource usage (low idle
time for processors).
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Taxonomy: Dynamic
Arrival times unpredictable
Static (compile-time) analysis possible
only for simple cases.
Processor utilization decreases
dramatically.
In many real systems, this is very
difficult to handle.
Must avoid over-simplifying assumptions
e.g., assuming that all tasks are
independent, when this is unlikely.
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Taxonomy: Periodic
Each task (or group of tasks) executes
repeatedly with a particular period.
Allows some static analysis techniques
to be used.
Matches characteristics of many real
problems
It is possible to have tasks with
deadlines smaller, equal to, or greater
than their period.
The later are difficult to handle (i.e., multiple
concurrent task instances occur).
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Periodic
Single rate:
One period in the system
Simple but inflexible
Used in implementing a lot of wireless
sensor networks.
Multi rate:
Multiple periods
Should be harmonics to simplify system
design
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Taxonomy: Aperiodic
Are also called sporadic,
asynchronous, or reactive.
Creates a dynamic situation
Bounded arrival time interval are
easier to handle
Unbounded arrival time intervals are
impossible to handle with resourceconstrained systems.
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Demo video
Control system
Hard Real Time
Multi-rate periodic
Camera
GPS
Low-speed mode for
rush hour traffic
United States Patent 7096109
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Video capture.
Digital filtering.
Video and voice compression/decompression.
Radar signal processing.
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Other Real-Time
Applications
Real-time databases.
Multimedia.
Want to process audio and video frames at steady rates.
TV video rate is 30 frames/sec. HDTV is 60 frames/sec.
Telephone audio is 16 Kbits/sec. CD audio is 128 Kbits/sec.
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Example: Interactive/Multimedia
Applications
Requirements
(performance, scale)
Interactive
Video
insufficient
resources
The
Theinterestin
interesti
real-time
real-time
applications
applications
are
arehere
here
sufficient
but scarce
resources
High-quality
Audio
Network
File Access
abundant
resources
Remote
Login
1980
1990
2000
Hardware resources in year X
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OS or not?
User Programs
Operating
Hardware
System
Typical OS Configuration
User Program
Including Operating
Hardware
System Components
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Foreground/Background
Systems
Task-level, interrupt
level
Critical operations
must be performed
at the interrupt level
(not good)
Response
time/timing depends
on the entire loop
Code change affects
timing
Simple, low-cost
systems
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RTS Programming
Concurrent programming
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Classification of Scheduling
Algorithms
All scheduling algorithms
static scheduling
(or offline, or clock driven)
dynamic scheduling
(or online, or priority driven)
static-priority
scheduling
dynamic-priority
scheduling
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Scheduling strategies
Non pre-emptive scheduling
Once a process has been scheduled for execution, it
runs to completion or until it is blocked for some reason
(e.g. waiting for I/O).
Pre-emptive scheduling
The execution of an executing processes may be
stopped if a higher priority process requires service.
Scheduling algorithms
Round-robin;
Rate monotonic;
Shortest deadline first;
Etc.
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Operating system
components
Real-time clock
Provides information for process scheduling.
Interrupt handler
Manages aperiodic requests for service.
Scheduler
Chooses the next process to be run.
Resource manager
Allocates memory and processor resources.
Dispatcher
Starts process execution.
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Interrupt servicing
Control is transferred automatically to a
pre-determined memory location.
This location contains an instruction to jump to
an interrupt service routine.
Further interrupts are disabled, the interrupt
serviced and control returned to the interrupted
process.
Interrupt service routines MUST be short,
simple and fast.
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High throughput
Schedulability
Responsiveness
Ensured worst-case
response
Overload
Fairness
Stability
Limited Resources
Common Component based software engineering
(CBSE) technologies (JavaBeans, CORBA and COM) are
seldom used as they:
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Program
Variable
access path
Resource
Task
Task
Program
Program
Task
Program
FB
FB
Function
Block
FB
FB
Variable
FB
Execution
control path
Access path
Communication Function
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Instruction lists
Assembly languages
Structured text
Ladder diagrams
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A Port-based Object
Configuration parameters
Variable
input ports
Port-based object
Variable
output ports
Page 44
Top-level design
Component
library
Detailed design
Architecture analysis
Scheduling / interface
check
Add new
components
to library
Obtain components
timing behavior on
target platform
System verification
Final product
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Top-level Design
The first stage of the development process involves decomposition of the system into manageable components
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Detailed Design
At this stage a detailed component design is performed,
by selecting components to be used from the candidate
set.
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Architecture Analysis
At this stage it is time to check that the system under
development satisfies extra-functional requirements
such as:
Maintainability
Reusability
Modifiability
Testability
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Scheduling
At this point we must check that the temporal
requirements of the system can be satisfied, assuming
time budgets assigned in the detailed design stage.
In other words, we need to make a schedulability
analysis of the system based on the temporal
requirements of each component
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WCET Verification
Performing a worst-case analysis can either be based
on measurements or on a static analysis of the
source code.
What is more interesting in the test cases is the
execution time behavior shown as a function of input
parameters as shown in the following slide.
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Execution time
domain 1
domain 2
domain 3
Input
Page 51
Execution time
domain 1
domain 2
domain 3
Input
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Component Library
Is the most central part of any CBSE system as it
contains binaries of components and their descriptions.
A component library containing real-time components
should provide the following:
Memory requirements
Dependencies
Environment assumptions
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Composition of Components
New Component (Cnew)
in1_Cnew
in_C1
Component 1
(C1)
in2_Cnew
in3_Cnew
in4_Cnew
out_C1
in2_Cn
Component n
(C2)
out1_Cn
out1_Cnew
out2_Cn
out2_Cnew
in1_C2
in2_C2
Component 2
(C3)
out_C2
out3_Cnew
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End-To-End Deadlines
End-to-end deadlines
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RT Components in Rubus OS
Rubus:
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oil pressure
speed
.
Task:
BrakeLeftRight
Period:
50 ms
Release time: 10 ms
Deadline:
30 ms
Precedes:
outputBrakeValues
WCET:
2 ms
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State information
brake left wheel
oil pressure
speed
State information
Component:
BrakeLeftRight
input 1
input 2
Component:
OutputBrakeValues
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Component: BrakeSystem
Task state information
pressure
oil
pressure
speed
brake left
Task:
BrakeLeftRight
brake right
Task:
OutputBrakeValues
speed
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Conclusion
The Rubus component model (CBSE)
provides:
Methods to express the infrastructure of
software functions, i.e., the interaction
between software functions in terms of dataflow and control-flow
The resulting architecture is formal enough for
analysis of timing and memory properties
The components and the infrastructure allow
for a resource efficient mapping onto a runtime structure
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