NETWORK

SYNCHRONIZATION:
CONTROL AND
MANAGEMENT

TIMING
Frequency source (clock) as a means
of timing internal and external
operations
Problem with transfers between one
synchronous equipment with the
other.
e.g A transmitter and a receiver
Short term variations jeopardize
integrity of data transfer
Hence, necessary to use stable

TIMING RECOVERY: PHASE LOCKED

LOOP
PLL to synchronize the receiver clock with
the transmitter.
Phase detector measures phase difference
between the incoming and locally
generated clock
Output of phase detector filtered to
minimize receive noise and interference on
the link.
This adjusts the frequency of the VCO to
reduce the phase difference.

PLL CLOCK RECOVERY

CIRCUIT

PLL TIMING RECOVERY

Some amount of noise inevitably
passes through LPF causing
erroneous adjustment in VCO
frequency.
Long term variations are averted as
the ever-increasing phase shifts
adjust the VCO freq.
Short term variations in phase and
freq. as it hunts down the underlying
clock frequency.

CLOCK INSTABILITY
Variation in output freq. of VCO corresponds
to clock instability
Even free-running oscillators have this.
Important aspect of the clock instability is its
frequency; the rate at which the clock
frequency changes from too high to too low
When VCO control voltage varies slowly
clock wander
When VCO control voltage varies rapidly jitter

Main sources of clock

instability
1. Noise and interference
2. Changes in the length of
transmission media
3. Changes in velocity of propagation
4. Doppler shifts from mobile terminals
5. Irregular timing information

Noise and Interference

Arbitrary LPF cannot be used for the following reasons
If the PLL begins oscillating at the wrong frequency and
bandwidth is too narrow, the PLL may never pull the
oscillator to the clock frequency(solution: use a wide one
for sync and then a narrow one after lock is achieved).
Source may vary in frequency and may not be tracked by
a slowly responding PLL.
Instability of the VCO itself. If VCO drifts in frequency and
very low bandwidth filters are slow to respond, they cant
adjust the VCO i/p voltage soon enough.
Also, systematic jitter (such as ISI) can have arbitrarily low
frequencies.

Noise and Interference Contd.

Accumulation of jitter
If the recovered clock is used to time the
transmission of outgoing data, such as a
regenerative repeater, some amount of
jitter passes on to the outgoing block.
Jitter accumulates at every repeater and
can accumulate to a point where the clock
recovery circuits have a problem tracking
receive clock, producing sampling errors
and possible lose of lock

Changes in Length of Transmission

Media
Thermal expansion or contraction of
guided transmission media or of
atmospheric bending of a radio path.
Increase in length reduces the bitrate at the receiver as more and
more bits are stored in the medium.
Significant path length changes
occur in satellite commn.

Changes in the Velocity of

propagation
Temperature changes -> Propagation
constants change -> Velocity of
propagation changes
Resulting changes in the clocking
stability is much lesser than that
caused by the change in path length.
Again, number of bits stored in the
transmission path is changed.

Doppler shifts
Most significant source of timing
instability occurs due to Doppler
shifts from satellites.
Digital mobile telephones receivers
must accommodate Doppler shifts
equivalent to clock instabilities of
about one part in 10^7.
Again, Doppler shifts occur in
essence, as a result of path changes.

Irregular Timing lnformation

A fundamental requirement of line code is to
provide sufficient timing information.
If timing information is data dependent, then
jitter can increase during phases of low density
in data information.
Higher level digital multiplexers inserting
overhead data, when de-multiplexed, the
arrival rate of data in the individual channels is
irregular and produces timing jitter when
generating new line clocks for lower rate
signals (discussed later)

ELASTIC STORE
Timing instability essentially change the
number of bits stored in transmission medium
In the case of noise and interference induced
jitter, number of bits stored changes due to
changes in sampling rate.
If phase offsets in successive repeaters
coincide, a net change of several bits in
storage and account for accumulated jitter
representing relatively large, but short lived,
instability of the clock.

ELASTIC STORE
Repeaters -> Incoming (locally derived)
sample clock as output clock
End receivers -> Local clock
An elastic store is a data buffer written
onto, by one clock, and read from, by
another.
Elastic store absorbs short term instabilities
that produce a limited difference in amount
of data transmitted and received.

Interface between TDM transmission

link and a digital switch using an
elastic
store.

TDM Switch Interface

The elastic store is placed between the incoming digital
transmission link and the inlet side of the switch.
Digital switches provide timing for TDM links so that
there is no timing discrepancy.
Far end of the digital link derives its clock from the
receive signal and uses this clock to time digital
transmissions returning to the switch (loop timing).
Elastic store absorbs instabilities so that purely
synchronized data is available for the switch.
Loop formed by elastic store and transmission links
maintains a constant and integral number of clock
intervals between inlet and outlet of the switch.

Elastic Store to remove accumulated

jitter in regenerative repeaters
Transmit timing is defined by a separate local
clock (usually from locally derived sample
clock).
The elastic store absorbs short term instabilities
in the receive clock.
Long-term frequency controlled by maintaining
a certain average level of storage.
If the elastic store is large enough to
accommodate all short-term transient
variations, high frequency clock instability is
removed.

Jitter-removing re-generative
repeater

Mechanism in Regenerative
Repeaters
Derive their output clocks by
averaging the incoming timing
information.
PLL does so for many intervals;
An elastic store increases the
available delay so that output timing
adjustments can be made more
gradually.
Jitter not only occurs in digital
transmission systems but also digital

Elastic Storage
Implementation
Size -> varies between a few bits to several
hundred (for long-distance communication)
Incoming data is transferred into the register
as soon as each word is accumulated in S-P.
Sometime later, this data is transferred onto
P-S converter (independent of the incoming
clock)
Short-term jitter hence absorbed in the
elastic store.

Basic implementation of an elastic

store

Elastic store implementation

Relative times of the parallel transfers into
and out of the holding register provides a
direct indication of the relative phase of the
input and output clocks.
Thus we have the information needed to
generate the VCO control voltage if the
elastic store has to remove accumulated
transmission jitter.
FIFO buffer can be used in place of the
register.

Circuit for measuring timing

jitter

JITTER MEASUREMENT
PLL with the phase comparator output
providing the measurement for timing jitter.
Bandwidth of LPF is very small so that the
VCO ignores short-term jitter.
If there is no jitter, output of phase
comparator is constant and no signal is
passed through the HPF.
Very low frequency jitter cannot be
measured; however, not a concern as PLL
will track it.

JITTER MEASUREMENT
High frequency jitter causes sampling errors
or loss of lock.
Both spectral content and magnitude of the
jitter are of interest.
Phase jitter power -> measure of variance of
number of clock cycles.
RMS power of phase comparator is
proportional to RMS phase jitter.
K_d -> phase detector gain factor in V/rad.