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COMPUTER ARCHITECTURE
A PRESENTATION ON MEMORY HIERARCHY
(MAIN MEMORY)
GROUP 1
FACULTY OF INFORMATICS
Group Members
Ishmael Haywoode
040116403
David Ayeliba
040116409
INTRODUCTION
The Memory Hierarchy is a concept used to discuss
performance issues in computer architectural design,
algorithm predictions, and lower level programming
constructs involving locality of reference. The memory
hierarchy in computer storage separates each of its
levels based on response time. Since response time,
complexity, and capacity are related, the levels may also
be distinguished by their performance and controlling
technologies.
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An Example Memory
Hierarchy
Smaller,
faster,
and
costlier
(per byte)
storage
devices
Larger,
slower,
and
cheaper
(per byte)
storage
devices
L5:
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L0:
L1:
L2:
L3:
L4:
registers
on-chip L1
cache (SRAM)
off-chip L2
cache (SRAM)
main memory
(DRAM)
Static RAM
Fast access time (used for off-processor cache)
Does not have to be refreshed
Dynamic RAM
Slower access time
Must be refreshed
much more dense
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Static RAM
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10
Dynamic RAM
addr
(to CPU)
2 bits
/
rows
memory
controller
1
supercell
(2,1)
2
8 bits
/
data
internal row buffer
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12
Reading DRAM
Supercell
(2,1)
Step 1(a): Row address
strobe (RAS) selects row 2
Step 1(b): Row 2 copied from DRAM array to row buffer
16 x 8 DRAM chip
0
RAS = 2
2
/
addr
rows
memory
controller
cols
1
2
8
/
data
CAS = 1
2
/
rows
memory
controller
supercell
(2,1)
addr
To CPU
cols
1
2
8
/
data
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supercell
(2,1)
15
8M x 32 (32MB) SIMM
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16
Levels of Performance
Recall:
Dynamic Random Access Memory (DRAM)
Capacitors to store state (0 or 1)
Periodically refreshed
Relatively cheap
17
BALANCING PERFORMANCE
WITH COST
Small memories
are fast but
expensive
Large memories are slow but
Persistence
cheap
Storing
data for lengthy periods of time
DRAM/SRAM is volatile: contents lost if power
lost
Disks are non-volatile: contents survive power
outages
To be useful, it must also be possible to find it
again later
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18
this brings in many interesting data organization,
OTP
RO
M
UVEPR
OM
EEPRO
M
FLASH
MEMOR
Y
CACH
E
SRAM
SSRA
M
Volatile
DRA
M
SDRA
MM
x
x
Quartz-glass window
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Highest Density
Fusible Links
x
x
x
X
19
THANK YOU
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