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CMOS VLSI
Design
Interconnect
Outline
Introduction
Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Wire Engineering
Repeaters
Interconnect
Slide 2
Introduction
Chips are mostly made of wires called interconnect
In stick diagram, wires set size
Transistors are little things under the wires
Many layers of wires
Wires are as important as transistors
Speed
Power
Noise
Alternating layers run orthogonally
Interconnect
Slide 3
Wire Geometry
Pitch = w + s
Aspect ratio: AR = t/w
Old processes had AR << 1
Modern processes have AR 2
Pack in many skinny wires
t
h
Interconnect
Slide 4
Layer Stack
AMI 0.6 m process has 3 metal layers
Modern processes use 6-10+ metal layers
Layer
T (nm) W (nm) S (nm) AR
Example:
6
1720
860
860
2.0
Intel 180 nm process
1000
M1: thin, narrow (< 3)
5
1600
800
800
2.0
High density cells
1000
4
1080
540
540
2.0
M2-M4: thicker
700
3
700
320
320
2.2
For longer wires
700
2
700
320
320
2.2
700
M5-M6: thickest
1
480
250
250
1.9
800
For VDD, GND, clk
CMOS VLSI Design
Substrate
Interconnect
Slide 5
Wire Resistance
= resistivity (*m)
Interconnect
Slide 6
Wire Resistance
= resistivity (*m)
l
R
t w
Interconnect
Slide 7
Wire Resistance
= resistivity (*m)
l
l
R
RW
t w
w
l
w
t
1 Rectangular Block
R = R (L/W)
4 Rectangular Blocks
R = R (2L/2W)
= R (L/W)
Interconnect
Slide 8
Choice of Metals
Until 180 nm generation, most wires were aluminum
Modern processes often use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Molybdenum (Mo)
5.3
CMOS VLSI Design
Interconnect
Slide 9
Sheet Resistance
Typical sheet resistances in 180 nm process
Layer
Diffusion (silicided)
3-10
50-200
Polysilicon (silicided)
3-10
50-400
Metal1
0.08
Metal2
0.05
Metal3
0.05
Metal4
0.03
Metal5
0.02
Metal6
0.02
CMOS VLSI Design
Interconnect
Slide 10
Contacts Resistance
Contacts and vias also have 2-20
Use many contacts for lower R
Many small contacts for current crowding around
periphery
Interconnect
Slide 11
Wire Capacitance
Wire has capacitance per unit length
To neighbors
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
s
w
layer n+1
h2
Ctop
t
h1
layer n
Cbot
Cadj
layer n-1
CMOS VLSI Design
Interconnect
Slide 12
Capacitance Trends
Parallel plate equation: C = A/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
= k0
0 = 8.85 x 10-14 F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
k 3 (or less) as dielectrics use air pockets
CMOS VLSI Design
Interconnect
Slide 13
M2 Capacitance Data
Typical wires have ~ 0.2 fF/m
Compare to 2 fF/m for gate capacitance
400
350
300
M1, M3 planes
s = 320
s = 480
s=
200
s = 640
Isolated
s = 320
150
s = 480
s = 640
100
s=
Ctotal (aF/m)
250
50
0
0
500
1000
1500
2000
w (nm)
Interconnect
Slide 14
Interconnect
Slide 15
R/N
R/N
C/N
C/N
R
C
L-model
C/2
R/N
R/N
C/N
C/N
R/2 R/2
C/2
-model
C
T-model
Interconnect
Slide 16
Example
Metal2 wire in 180 nm process
5 mm long
0.32 m wide
Construct a 3-segment -model
R =
Cpermicron =
Interconnect
Slide 17
Example
Metal2 wire in 180 nm process
5 mm long
0.32 m wide
Construct a 3-segment -model
R = 0.05 /
=> R = 781
Cpermicron = 0.2 fF/m
=> C = 1 pF
260
260
260
167 fF 167 fF
167 fF 167 fF
167 fF 167 fF
Interconnect
Slide 18
Wire RC Delay
Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example.
R = 2.5 k*m for gates
Unit inverter: 0.36 m nMOS, 0.72 m pMOS
tpd =
CMOS VLSI Design
Interconnect
Slide 19
Wire RC Delay
Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example.
R = 2.5 k*m for gates
Unit inverter: 0.36 m nMOS, 0.72 m pMOS
781
500 fF 500 fF
690
tpd = 1.1 ns
Driver
Wire
4 fF
Load
Interconnect
Slide 20
Crosstalk
A capacitor does not like to change its voltage
instantaneously.
A wire has high capacitance to its neighbor.
When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
Called capacitive coupling or crosstalk.
Crosstalk effects
Noise on nonswitching wires
Increased delay on switching wires
Interconnect
Slide 21
Crosstalk Delay
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
A
Miller effect
Cgnd
Ceff(A)
Cadj
B
Cgnd
MCF
Constant
Switching with A
Switching opposite A
CMOS VLSI Design
Interconnect
Slide 22
Crosstalk Delay
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
A
Miller effect
Cgnd
Ceff(A)
MCF
Constant
VDD
Cgnd + Cadj
Switching with A
Cgnd
Switching opposite A
Cadj
B
Cgnd
Interconnect
Slide 23
Crosstalk Noise
Crosstalk causes noise on nonswitching wires
If victim is floating:
model as capacitive voltage divider
Vvictim
Cadj
C gnd v Cadj
Vaggressor
Aggressor
Vaggressor
Cadj
Victim
Cgnd-v
Vvictim
Interconnect
Slide 24
Driven Victims
Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
Victim driver is in linear region, agg. in saturation
If sizes are same, Raggressor = 2-4 x Rvictim
Vvictim
Cadj
C gnd v Cadj
1
Vaggressor
1 k
Raggressor
Cgnd-a
Vaggressor
victim
Rvictim Cgnd v Cadj
CMOS VLSI Design
Aggressor
Cadj
Rvictim
Victim
Cgnd-v
Vvictim
Interconnect
Slide 25
Coupling Waveforms
Simulated coupling for Cadj = Cvictim
Aggressor
1.8
1.5
1.2
Victim (undriven): 50%
0.9
0.6
0.3
0
0
200
400
600
800
1000
1200
1400
1800
2000
t(ps)
Interconnect
Slide 26
Noise Implications
So what if we have noise?
If the noise is less than the noise margin, nothing
happens
Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
But glitches cause extra delay
Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can
produce the wrong answer
CMOS VLSI Design
Interconnect
Slide 27
Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
Interconnect
Slide 28
Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
Width
Spacing
0.8
1.8
0.7
2.0
1.6
Delay (ns):RC/2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
0.4
0.3
0.2
0.1
0
500
1000
1500
2000
Pitch (nm)
WireSpacing
(nm)
320
480
640
0.5
500
1000
1500
2000
Pitch (nm)
Interconnect
Slide 29
Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
Width
Spacing
Layer
0.8
1.8
0.7
2.0
1.6
Delay (ns):RC/2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
0.4
0.3
0.2
0.1
0
500
1000
1500
2000
Pitch (nm)
WireSpacing
(nm)
320
480
640
0.5
500
1000
1500
2000
Pitch (nm)
Interconnect
Slide 30
Wire Engineering
Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
Width
Spacing
Layer
Shielding
0.8
1.8
0.7
2.0
1.6
Delay (ns):RC/2
1.4
1.2
1.0
0.8
0.6
0.4
0.6
0.4
0.3
0.2
0.2
0
0.1
0
500
1000
1500
2000
1000
500
a1 gnd a2
a3 vdd
1500
2000
Pitch (nm)
Pitch (nm)
vdd a0
WireSpacing
(nm)
320
480
640
0.5
a0
b0
a1
b1
a2
b2
Interconnect
Slide 31
Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires
Interconnect
Slide 32
Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with an inverter or buffer
Wire Length: l
Driver
Receiver
N Segments
Segment
l/N
Driver
l/N
Repeater
l/N
Repeater
Repeater
Receiver
Interconnect
Slide 33
Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
Wire length l/N
Wire Capaitance Cw*l/N, Resistance Rw*l/N
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C*W, Resistance R/W
Interconnect
Slide 34
Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
Wire length l
Wire Capacitance Cw*l, Resistance Rw*l
Inverter width W (nMOS = W, pMOS = 2W)
Gate Capacitance C*W, Resistance R/W
RwlN
R/W
Cwl/2N Cwl/2N
CMOS VLSI Design
C'W
Interconnect
Slide 35
Repeater Results
Write equation for Elmore Delay
Differentiate with respect to W and N
Set equal to 0, solve
2 RC
RwCw
N
t pd
l
W
2 2
RC RwCw
~60-80 ps/mm
in 180 nm process
RCw
RwC
CMOS VLSI Design
Interconnect
Slide 36