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Basic Electronic

Engineering
Chapter 6:
Field Effect Transistors
Instructor: Fahd Naveed Cheema
Email: fahd.cheema@cust.edu.pk
Office Timings: Monday 11 AM - 1 PM
Fahd Cheema

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Outline
Introduction to & different types of FET:
JFET (Junction Field Effect)
MOSFET (Metal-Oxide Semiconductor FET)
MESFET (Metal-Semiconductor FET)

Construction, Characteristics & Transfer


Curves of JFET & MOSFET

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FETs vs. BJTs: Similarities


Amplifiers
Switching devices
Impedance matching circuits

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FETs vs. BJTs: Differences


FETs are voltage controlled devices. BJTs are current
controlled devices.

FETs have higher input impedance. BJTs have higher


gain.
FETs are generally more static sensitive than BJTs.
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FETs vs. BJTs: Differences


The BJT is a bipolar device, which means
that the conduction level is a function of two
charge carriers; electrons & holes.
The FET is a unipolar device, depending
solely on either electrons or holes.
Av of BJT is much greater than that of FET.

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FETs vs. BJTs: Differences


FETs are more temperature stable
than BJTs, and smaller than BJTs,
making them particularly useful in
integrated circuit (IC) chips.
For BJT, the IC is a direct function of IB;
for FET, ID will be a function of the VGS.
In both cases, output current is
controlled by an input parameter.
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FET
The term field effect:
an electric field is established by the charges
present, which controls the conduction path of the
output circuit without direct contact between the
controlling and controlled quantities.

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FET Types
JFET: Junction FET
MOSFET: MetalOxideSemiconductor FET
D-MOSFET: Depletion MOSFET
E-MOSFET: Enhancement MOSFET

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JFET Construction
There are two types of JFETs:
1. n-channel
2. p-channel
The n-channel is the more widely used.

JFETs have three terminals:


The Drain (D) and Source (S) are
connected to the n-channel.

The Gate (G) is connected to the p-type material.


In the absence of any applied potentials the JFET has two p n junctions under
no-bias conditions. The result is a depletion region at each junction, as shown
in Fig. that resembles the same region of a diode under no-bias conditions.
A depletion region is void of free carriers and is therefore unable to support
conduction.
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JFET Operation: The Basic Idea


JFET operation can be compared to that of a water spigot.
The source is the accumulation of
electrons at the negative pole of the
drain-source voltage.
The drain is the electron deficiency
(or holes) at the positive pole of the
applied voltage.
The gate controls the width of the nchannel and, therefore, the flow of
charges from source to drain.
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JFET Construction & Operation

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JFET Operating Characteristics


There are three basic
operating conditions
for a JFET:
VGS = 0 V, VDS > 0
VGS < 0 V, VDS > 0
Voltage-controlled resistor

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JFET Characteristics:
VGS = 0V, VDS > 0V
As shown in the figure, a positive voltage
VDS ( = VDD) is applied across the
channel.
The gate is connected directly to the
source to establish the condition VGS = 0.
The electrons are drawn to the drain,
leading to the current ID, which is also
the same as IS (i.e. ID = IS).
And ID is solely limited by the resistance
of the n-channel between D & S.
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JFET Characteristics:
VGS = 0V, VDS > 0V
The depletion region is wider near the
top of both p-type materials.
The reason is that upper region is more
reverse-biased than the lower part,
thus a wider depletion region.
The p-n junction is reverse-biased for
the whole length of the channel,
leading to no current in the gate
terminal (IG = 0 ).
IG = 0 is an important characteristic of
JFET.
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JFET Characteristics:
VGS = 0V, VDS > 0V
3 things happen when VGS = 0V & VDS > 0V :
1. The size of the depletion region between
p- type gate & n-channel increases.
2. Increasing the size of the depletion region
decreases the width of the n-channel,
which increases its resistance.
3.Even though the n-channel resistance is
increasing, the current from source to drain
(ID) through the n-channel is increasing
because VDS is increasing.
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JFET Characteristics:
VGS = 0V, VDS > 0V
The depletion region is wider near the top of both
p type materials.
Assuming a uniform resistance in the n-channel, we
can break down the resistance of the channel into the
divisions appearing in Fig. 6.6.
The current ID will establish the voltage levels
through the channel as indicated on the same figure.
The result is that the upper region will be more
reverse-biased than the lower region.
From diode operation; greater the applied reverse
bias, the wider is the depletion regionhence the
distribution of the depletion region as shown in Fig. 6.6.
The fact that the p n junction is reverse-biased for
the length of the channel results in a gate current
of 0A.
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JFET Characteristics: Pinch Off


If VGS = 0V & VDS continually increases to a
more positive voltage, a point is reached
where the depletion region gets so large that
it pinches off or touches the channel.
This suggests that the current in channel (ID)
drops to 0A, but it does not. As VDS increases,
so does ID. However, once pinch off occurs,
further increases in VDS do not cause ID to
increase.
In reality a very small channel still exists with
a current of very high density.

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JFET Characteristics: Saturation


At the pinch-off point:
Any further increase in VDS does
not produce any increase in ID.
VDS at pinch-off is denoted as Vp.
ID at saturation or maximum is
referred to as IDSS.
Once VDS > VP the JFET has the characteristics of a current source.
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Equivalent Circuit at
VGS = 0V, VDS > 0V
As VDS is increased beyond VP , the region of
close encounter between the two depletion
regions increases in length along the channel,
but the level of ID remains essentially the same.
As shown in Fig, the current is fixed at ID = IDSS, but
the voltage VDS (for levels > VP) is determined by
the applied load.
IDSS is the drain-to-source current with a shortcircuit connection from gate to source.
IDSS is the maximum drain current for a JFET and
is defined by the conditions VGS = 0V and
VDS > VP .
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JFET Characteristics: VGS < 0V


The voltage from gate to source, denoted
by VGS, is the controlling voltage of JFET.
For the n - channel device the controlling
voltage VGS is made more and more
negative from its VGS = 0V level.
In other words, the gate terminal will be
set at lower and lower potential levels as
compared to the source.
As VGS becomes more negative, the
depletion region increases.
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JFET Characteristics: VGS < 0V


A negative voltage of 1V is applied between the
gate and source terminals for a low level of V DS.
The effect of the applied negative-bias VGS is to
establish depletion regions similar to those
obtained with VGS = 0V, but at lower levels of
VDS.
Therefore, the result of applying a negative
bias to the gate is to reach the saturation
level at a lower level of VDS .

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JFET Characteristics: VGS < 0V


As VGS becomes more negative:
The JFET experiences pinch
- off at a lower voltage (VP).
ID decreases (ID < IDSS) even
when VDS increases.
ID eventually drops to 0mA.
The value of VGS that
causes this to occur is
designated VGS(off).
At high levels of VDS the JFET reaches a breakdown situation.
ID increases uncontrollably if VDS >VDSmax, and the JFET is likely destroyed.
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Voltage-Controlled Resistor: VGS < 0V


The region to the left of the
pinch-off point is called the
ohmic region or voltagecontrolled resistance region.
JFET can be used as a variable
resistor, where VGS controls the
drain-source resistance (rd).

ro is the resistance with VGS = 0V,


rd is the resistance at a particular
level of VGS.

Example:
For an n -channel JFET with ro = 10 k (VGS = 0V,
VP = -6 V), Eq. results in rd = 40k at VGS = -3V.
As VGS becomes more negative, the resistance (rd) increases.

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P-Channel JFETs
The
p-channel
JFET
behaves the same as the nchannel JFET.
The only
differences are that the
voltage polarities and current
directions are reversed.

For the p -channel device, the


channel will be constricted by
increasing positive voltages
from gate to source.
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P-Channel JFET Characteristics


As VGS becomes more positive:
The JFET experiences pinch-off
at a lower voltage (VP).
The depletion region increases,
and ID decreases (ID < IDSS)
ID eventually drops to 0 mA
(when VGS = VGSoff)
Also note that at high levels of VDS the JFET reaches a breakdown situation.
ID increases uncontrollably if VDS > VDSmax.
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JFET Symbols

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Summary

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JFET Transfer Characteristics


JFET input-to-output transfer characteristics are not
as straightforward as they are for a BJT.
BJT: indicates the relationship between IB (input) and IC
(output).
JFET: The relationship of VGS (input) and ID (output) is a little
more complicated:

Shockleys equation:

I D I DSS

VGS
VP

where the IDSS and VP are constants, and VGS controls the ID.
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BJT

JFET

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JFET Transfer Curve

This graph shows the value of ID for a given value of VGS.


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Plotting the JFET Transfer Curve


Using IDSS and Vp (VGS(off)) values found in a specification sheet, the
transfer curve can be plotted according to these three steps:
1. Solving for VGS = 0 V: ID = IDSS
2. Solving for VGS = VGS(off):

ID = 0 A

ID I

1VGS
DSS
VP

3. Solving for VGS = 0 V to VGS(off): 0 A < ID < IDSS

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JFET Transfer Characteristics


The transfer characteristics are properties of
JFET itself and are unaffected by the
network in which the device is used.
The transfer characteristics can be obtained
by Shockleys equation.
It can also be obtained from the output drain
characteristics.
We draw both curves with a common
vertical scaling.
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JFET Transfer Characteristics


One is a plot of ID versus VDS , whereas the
other is ID versus VGS.
Using the drain characteristics on the right of
the vertical axis, we can draw a horizontal line
from the saturation region of the curve to the I D
axis.
The result current level for both graphs is I DSS.
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JFET Transfer Characteristics


The point of intersection on the ID versus VGS
curve will be as shown since the vertical axis
is defined as VGS = 0.
If a horizontal line is drawn from the VGS=-1V
curve to the ID axis and then extended to the
other axis, another point on the transfer
curve can be located.
Continuing with VGS = -2V, -3V and VP (-4V),
we can complete the transfer curve.

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JFET Transfer Curve

This graph shows the value of ID for a given value of VGS.


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JFET Transfer Characteristics


The transfer curves are useful and there are ways to plot it:

1. By Shockleys equation, its precise but the


calculation is time-consuming.
2. By the drain characteristics, its not easy since
the drain characteristics should be known first.
3. Here, a shorthand method will plot the curve in a
efficient manner while maintaining an acceptable
degree of accuracy.
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Shorthand Method

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Shorthand Method

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VGS versus ID Using


Shockleys Equation

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JFET Transfer Characteristics

Figure: Transfer curve by shorthand method


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Example 6.1

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P-Channel JFET
Transfer Characteristics
For p-channel devices, Shockleys equation
can still be applied exactly as it appears.
In this case, both VGS and VP will be positive.
The transfer characteristics will be the mirror
image of the transfer curve obtained with an nchannel and the same limiting values.
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P-Channel JFET
Transfer Characteristics

Figure: Transfer curve of p-channel JFET


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Example 6.2

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Important Relationships

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Important Conclusions

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SELF STUDY TOPICS

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Basic MOSFET Operation


A depletion-type MOSFET can operate in two modes:

Depletion mode
Enhancement mode

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Depletion-Type MOSFET Construction


The Drain (D) and Source (S)
connect to the to n-type regions.
These
n-type
regions
are
connected via an n-channel. This
n-channel is connected to the
Gate (G) via a thin insulating
layer of silicon dioxide (SiO2).
The n-type material lies on a
p-type substrate that may have
an additional terminal connection
called the Substrate (SS).
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Depletion Mode Operation


(Depletion Type MOSFET)
The characteristics are
similar to a JFET.
When VGS = 0 V, ID = IDSS
When VGS < 0 V, ID < IDSS
The formula used to plot the transfer
curve for a JFET applies to a D-MOSFET
as well:
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ID I

1VGS
DSS
VP

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Enhancement Mode Operation


(Depletion Type MOSFET)
VGS > 0 V, ID increases
above IDSS (ID > IDSS)
The formula used to
plot the transfer curve
still applies:

ID I

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1VGS
DSS
VP

Note that VGS is now positive.

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p-Channel Depletion Type MOSFET

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Depletion Type MOSFET Symbols

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Enhancement Type
MOSFET Construction
The Drain (D) and Source (S) connect to the to n-type regions.
These n-type regions are connected via an n-channel.
The Gate (G) connects to the p-type
substrate via a thin insulating layer of
silicon dioxide (SiO2).
There is no channel.
The n-type material lies on a p-type
substrate that may have an additional
terminal connection called the
Substrate (SS).
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Enhancement Type
MOSFET Operation
The enhancement-type MOSFET (E-MOSFET) operates only
in the enhancement mode.
VGS is always positive.
As VGS increases, ID
increases.
As VGS is kept constant
and VDS is increased,
then ID saturates (IDSS)
and the saturation level
(VDSsat) is reached.
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Enhancement Type
MOSFET Transfer Curve
To determine ID given VGS:
ID k (VGS VT )2
where:
VT = the E-MOSFET
threshold voltage
k, a constant, can be
determined by using
values at a specific point
and the formula:
k

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VDSsat can be calculated using:


ID(ON)

(VGS(ON) VT)

VDSsat VGS VT

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p-Channel Enhancement
Type MOSFETs

The p-channel enhancement-type MOSFET is similar


to its n-channel counterpart, except that the voltage
polarities and current directions are reversed.
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MOSFET Symbols

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Handling MOSFETs
MOSFETs are very sensitive to static electricity.
Because of the very thin SiO2 layer between the external terminals
and the layers of the device, any small electrical discharge can
create an unwanted conduction.

Protection
Always transport in a static sensitive bag
Always wear a static strap when handling MOSFETS
Apply voltage limiting devices between the gate and source,
such as back-to-back Zeners to limit any transient voltage.
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VMOS Devices
VMOS (vertical MOSFET) is a component structure that
provides greater surface area.

Advantages
VMOS devices handle
higher
currents
by
providing more surface
area to dissipate the heat.
VMOS devices also have
faster switching times.
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CMOS Devices
CMOS (complementary MOSFET) uses a p-channel and
n-channel MOSFET; often on the same substrate as
shown here.
Advantages
Useful in logic circuit
designs
Higher input impedance
Faster switching speeds
Lower operating power
levels
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Thank You

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