LOGICSYNTHESIS

Verilog and logic synthesis

-VHDL and logic synthesis types of simulation -boundary
scan test - fault simulation automatic test pattern
generation.

 Logic synthesisprovides a link between an HDL

(Verilog or VHDL) and a netlist.
However, the parallel is not exact.
C was developed for use with compilers, but HDLs
were not developed for use with logic-synthesis
tools.
Verilog was designed as a simulation language and
VHDL was designed as a documentation and
description language.
Both Verilog and VHDL were developed in the early
1980s, well before the introduction of commercial
logic-synthesis software.
Because these HDLs are now being used for
purposes for which they were not intended, the state
of the art in logic synthesis falls far short of that for
computer-language compilers.
Logic synthesis forces designers to use a subset of

 When talking to a logic-synthesis tool using

an HDL, it is necessary to think like
hardware, anticipating the netlist that logic
synthesis will produce.
This situation should improve in the next five
years, as logic synthesizers mature.
Designers use graphic or text design entry to
create an HDLbehavioral model, which does
not contain any references to logic cells
State diagrams, graphical data path
descriptions, truth tables, RAM/ROM
templates, and gate-level schematics may
be used together with an HDL description.

Once a behavioural HDL model is complete, two

items are required to proceed:
A logic synthesizer(software and
documentation) and a cell library (the logic cells
NAND gates and such) that is called thetarget
library.
The behavioural model is simulated to check
that the design meets the specifications and
then the logic synthesizer is used to generate a
net list, astructural model, which contains only
references to logic cells.
There is no standard format for the net lists
that logic synthesis produces, but EDIF is widely
used.

Verilog and Logic Synthesis

A top-down design approach using Verilog begins with
a singlemoduleat the top of the hierarchy to model
the input and output response of the ASIC:
moduleMyChip_ASIC(); ... (code to model ASIC
I/O) ...endmodule;
This top-level Verilog module is used to simulate the
ASIC I/O connections and any bus I/O during the
earliest stages of design.
Often the reason that designs fail is lack of attention
to the connection between the ASIC and the rest of the
system.
As a designer, you proceed down through the
hierarchy as you add lower-level modules to the toplevel Verilog module

placeholders, orstubs, containing a minimum of

code.
For example, you might start by using inverters
just to connect inputs directly to the outputs.
You expand these stubs before moving down to
the next level of modules.
moduleMyChip_ASIC()
// behavioral "always", etc. ...
SecondLevelStub1 port mapping
SecondLevelStub2 port mapping
...endmodule
moduleSecondLevelStub1() ...assignOutput1 =
~Input1;endmodule
moduleSecondLevelStub2() ...assignOutput2 =
~Input2; endmodule

Eventually the Verilog modules will correspond to

Before we could start synthesis of the Viterbi

decoder we had to alter the model for the D flipflop.
This was because the original flip-flop model
contained syntax (multiplewaitstatements in
analwaysstatement) that was acceptable to the
simulation tool but not by the synthesis tool.
However, finding ourselves with nonsynthesizable code arises frequently in logic
synthesis.
The original OVI LRM included asynthesis policy,
a set of guidelines that outline which parts of the
Verilog language a synthesis tool should support
and which parts are optional.
There is no current standard on which parts of an
HDL (either Verilog or VHDL) a synthesis tool

D FLIP-FLOP
moduledff(D,Q,Clock,Reset); // N.B. reset is
active-low
outputQ;inputD,Clock,Reset;
parameterCARDINALITY = 1;reg[CARDINALITY-1:0]
Q;

wire[CARDINALITY-1:0] D;
always@(posedgeClock)if(Reset!==0)
#1 Q=D;
alwaysbeginwait(Reset==0);
Q=0;wait(Reset==1);end
endmodule

D FLIP-FLOP - MODEFIED
moduledff(D, Q, Clk, Rst); // new flip-flop for
Viterbi decoder
parameterwidth = 1, reset_value =
0;input[width - 1 : 0] D;
output[width - 1 : 0] Q;reg[width - 1 : 0]
Q;inputClk, Rst;
initialQ <= {width{1'bx}};
always@ (posedgeClkornegedgeRst )
if( Rst == 0 ) Q <= #1 reset_value;elseQ
<= #1 D;
endmodule

It is essential that the structural model created

by a synthesis tool isfunctionally identical,
orfunctionally equivalent, to your behavioral
model.
Hopefully, we know this is true if the synthesis
tool is working properly. In this case the logic is
correct by construction.
If you use different HDL code for simulation and
for synthesis, you have a problem.
The process offormal verificationcan prove that
two logic descriptions (perhaps structural and
behavioral HDL descriptions) are identical in their
behavior.

Delays in Verilog
Synthesis tools ignore delay values.
They musthow can a synthesis tool guarantee that logic
will have a certain delay?
For example, a synthesizer cannot generate hardware to
implement the following Verilog code:
moduleStep_Time(clk, phase);
inputclk;output[2:0] phase;reg[2:0] phase;
always@(posedgeclk)begin
phase <= 4'b0000;
phase <= #1 4'b0001; phase <= #2 4'b0010;
phase <= #3 4'b0011; phase <= #4 4'b0100;
end
endmodule

We can avoid this type of timing problem by

dividing a clock as follows:
moduleStep_Count (clk_5x, phase);
inputclk_5x;output[2:0] phase;reg[2:0]
phase;
always@(posedgeclk_5x)
case(phase)
0:phase = #1 1; 1:phase = #1 2; 2:phase = #1 3;
3:phase = #1 4;

default: phase = #1 0;
endcase
endmodule

Blocking and Nonblocking Assignments

There are some synthesis limitations that arise
from the different types of Verilog assignment
statements.
Consider the following shift-register model:
modulerace(clk, q0);inputclk, q0;regq1, q2;
always@(posedgeclk) q1 = #1
q0;always@(posedgeclk) q2 = #1 q1;
Endmodule
This example has arace condition(or arace) that
occurs as follows.
The synthesizer ignores delays and the
twoalwaysstatements are procedures that
execute concurrently

Inrealhardwaretwosignalswouldberacingeachotherandthewinner
isunclear.
Wemustthinklikethehardwaretoguidethesynthesistool.Combining
theassignmentstatementsintoasinglealwaysstatement,asfollows,
isonewaytosolvethisproblem:
moduleno_race_1(clk,q0,q2);inputclk,
q0;outputq2;regq1,q2;

always@(posedgeclk)beginq2=q1;q1=q0;end
Endmodule
We can also avoid the problem if we use nonblocking
assignment statements,
moduleno_race_2(clk, q0, q2);inputclk,
q0;outputq2;regq1, q2;
always@(posedgeclk) q1 <= #1
q0;always@(posedgeclk) q2 <= #1 q1;
endmodule
This code updates all the registers together, at the end of
a time step, soq2always gets the old value ofq1.

Combinational Logic in Verilog

To model combinational logic, the sensitivity list
of a Verilog always statement must contain only
signals with no edges (no reference to keywords
posedgeornegedge).
This is alevel-sensitivesensitivity listas in
the following example that implies a two-input
AND gate:
moduleAnd_Always(x, y,
z);inputx,y;outputz;regz;
always@(xory) z <= x & y; // combinational logic
method 1

endmodule
Continuous assignment statements also imply
combinational logic (notice thatzis now awirerather

 We may also use concatenation or bit reduction

to synthesize combinational logic functions,
moduleAnd_Or
(a,b,c,z);inputa,b,c;outputz;reg[1:0]z;
always@(aorborc)beginz[1]<= &{a,b,c};
z[2]<= |{a,b,c};end
endmodule
moduleParity (BusIn, outp);input[7:0]
BusIn;outputoutp;regoutp;
always@(BusIn)if(^Busin == 0) outp =
1;elseoutp = 0;
endmodule

 We may also use concatenation or bit reduction

to synthesize combinational logic functions,
moduleAnd_Or
(a,b,c,z);inputa,b,c;outputz;reg[1:0]z;
always@(aorborc)beginz[1]<= &{a,b,c};
z[2]<= |{a,b,c};end
endmodule
moduleParity (BusIn, outp);input[7:0]
BusIn;outputoutp;regoutp;
always@(BusIn)if(^Busin == 0) outp =
1;elseoutp = 0;
endmodule

 The number of inputs, the types, and the drive

strengths of the synthesized combinational logic
cells will depend on the speed, area, and load
requirements that you set as constraints.
moduleAnd_Bad(a, b, c);inputa, b;outputc;regc;
always@(a) c <= a & b; // b is missing from this
sensitivity list
endmodule

It is easy to write Verilog code that will simulate,

but that does not make sense to the synthesis
software. To avoid this type of problem with
combinational logic inside analwaysstatement
you should either:
include all variables in the event expression or
assign to the variables before you use them

Multiplexers In Verilog
We imply a MUX using acasestatement, as in the
following example:

moduleMux_21a(sel, a, b, z);inputsel, a , b;outputz;regz;

always@(aorborsel)
begin case(sel) 1'b0: z <= a; 1'b1: z <= b;end
endmodule

a synthesizer cannot make logic to model the following

and will usually issue a warning to that effect:
moduleMux_x(sel, a, b, z);inputsel, a,
b;outputz;regz;
always@(aorborsel)
begin case(sel) 1'b0: z <= 0; 1'b1: z <= 1; 1'bx: z
<= 'x';end
endmodule

VHDL and Logic Synthesis

Most logic synthesizers insist we follow a set of rules
when we use a logic system to ensure that what we
synthesize matches the behavioral description.
Here is a typical set of rules for use with the IEEE VHDL
nine-value system:
You can use logic values corresponding to
states'1','H','0', and'L'in any manner.
Some synthesis tools do not accept the uninitialized
logic state'U'.
You can use logic states'Z','X','W', and'-'in signal
and variable assignments in any manner.'Z'is
synthesized to three-state logic.
The states'X','W', and'-'are treated as unknown or
dont care values.

 The values'Z','X','W', and'-'may be

used in conditional clauses such as the
comparison in aniforcasestatement.
However, some synthesis tools will ignore
them and only match
surrounding'1'and'0'bits.
Consequently, a synthesized design may
behave differently from the simulation if
a stimulus uses'Z','X','W'or'-'.
The IEEE synthesis packages provide
theSTD_MATCHfunction for comparisons.

Initialization and Reset

You can use a VHDLprocesswith asensitivity list to
synthesize clocked logic with a reset, as in the following code:
process(signal_1, signal_2)begin
if(signal_2'EVENTandsignal_2 = '0')
then-- Insert initialization and reset statements.
elsif(signal_1'EVENTandsignal_1 = '1')
then-- Insert clocking statements.
endif;
end process;
Using a specific pattern the synthesizer can infer that you are
implying a positive-edge clock (signal_1) and a negativeedge reset (signal_2).
In order to be able to recognize sequential logic in this way,
most synthesizers restrict you to using a maximum of two
edges in a sensitivity list.

Combinational Logic Synthesis in VHDL

In VHDL alevel-sensitive processis
aprocessstatement that has a sensitivity list
with signals that are not tested for event
attributes ('EVENTor'STABLE, for example)
within theprocess.
To synthesize combinational logic we use a
VHDL level-sensitiveprocessor a concurrent
assignment statement.
Some synthesizers do not allow reference to a
signal inside a level-sensitiveprocessunless
that signal is in the sensitivity list

 entityAnd_Badis port(a, b:inBIT;

c:outBIT);endAnd_Bad;
architectureSynthesis_BadofAnd_Badis
begin process(a) -- this should be process
(a, b)
beginc <= aandb;
endprocess;
endSynthesis_Bad;
This situation is similar but not exactly the
same as omitting a variable from an event
control in a Verilogalwaysstatement.
Some logic synthesizers accept the VHDL
version ofAnd_Badbut not the Verilog version
or vice versa.

Multiplexers in VHDL
Multiplexers can be synthesized using acasestatement
(avoiding the VHDL reserved word'select'), as the
following example illustrates:
entityMux4is port(i: BIT_VECTOR(3downto0); sel:
BIT_VECTOR(1downto0); s:outBIT);
endMux4;
architectureSynthesis_1ofMux4is
beginprocess(sel, i)begin
caseselis
when"00" => s <= i(0);when"01" => s <= i(1);
when"10" => s <= i(2);when"11" => s <= i(3);
endcase;
endprocess;
endSynthesis_1;

 The following code, using a concurrent signal

assignment is equivalent:
architectureSynthesis_2ofMux4is
begin withselselects <=
i(0)when"00", i(1)when"01", i(2)when"10",
i(3)when"11";
endSynthesis_2;
In VHDL thecasestatement must be exhaustive
in either form, so there is no question of any
priority in the choices as there may be in Verilog.

For larger MUXes we can use an array, as in the following example:

libraryIEEE;useieee.std_logic_1164.all;
entityMux8is port
(InBus :inSTD_LOGIC_VECTOR(7downto0);
Sel :inINTEGERrange0 to 7;
OutBit :outSTD_LOGIC);
endMux8;
architectureSynthesis_1ofMux8is
beginprocess(InBus, Sel)
beginOutBit <= InBus(Sel);
endprocess;
endSynthesis_1;
Most synthesis tools can infer that, in this case,Selrequires three
bits. If not, you have to declare the signal as aSTD_LOGIC_VECTOR,
Sel :inSTD_LOGIC_VECTOR(2downto0);
and use a conversion routine from theSTD_NUMERICpackage like
this:
OutBit <= InBus(TO_INTEGER ( UNSIGNED (Sel) ) ) ;

Types of Simulation
Simulators are usually divided into the
following categories orsimulation modes:
Behavioral simulation
Functional simulation
Static timing analysis
Gate-level simulation
Switch-level simulation
Transistor-level or circuit-level simulation
This list is ordered from high-level to low-level
simulation (high-level being more abstract,
and low-level being more detailed).

Proceeding from high-level to low-level

simulation, the simulations become more
accurate, but they also become progressively
more complex and take longer to run.
There are several ways to create an imaginary
simulation model of a system.
One method models large pieces of a system as
black boxes with inputs and outputs.
This type of simulation (often using VHDL or
Verilog) is calledbehavioral simulation.
Functional simulationignores timing and
includesunit-delay simulation, which sets
delays to a fixed value (for example, 1 ns).

 Once a behavioral or functional simulation predicts that

a system works correctly, the next step is to check the
timing performance.
At this point a system is partitioned into ASICs and
atiming simulationis performed for each ASIC
separately
One class of timing simulators employstiming
analysisthat analyzes logic in a static manner,
computing the delay times for each path.
This is calledstatic timing analysisbecause it does not
require the creation of a set of test (or stimulus) vectors
(an enormous job for a large ASIC).
Timing analysis works best with synchronous systems
whose maximum operating frequency is determined by
the longest path delay between successive flip-flops.
The path with the longest delay is thecritical path.

 Logic simulationorgate-level simulationcan also

be used to check the timing performance of an
ASIC.
In a gate-level simulator a logic gate or logic cell
(NAND, NOR, and so on) is treated as a black box
modeled by a function whose variables are the
input signals.
The function may also model the delay through the
logic cell.
Setting all the delays to unit value is the equivalent
of functional simulation.
If the timing simulation provided by a black-box
model of a logic gate is not accurate enough, the
next, more detailed, level of simulation isswitchlevel simulationwhich models transistors as
switcheson or off.

 Switch-level simulation can provide more

accurate timing predictions than gate-level
simulation, but without the ability to use logiccell delays as parameters of the models.
The most accurate, but also the most complex
and time-consuming, form of simulation
istransistor-level simulation.
A transistor-level simulator requires models of
transistors, describing their nonlinear voltage
and current characteristics.
Each type of simulation normally uses a
different software tool.
Amixed-mode simulatorpermits different parts
of an ASIC simulation to use different
simulation modes.

Boundary-Scan Test
It is possible to test ICs in dual-in-line
packages (DIPs) with 0.1 inch (2.5 mm)
lead spacing on low-density boards using
abed-of-nails testerwith probes that
contact test points underneath the board.
Mechanical testing becomes difficult with
board trace widths and separations below
0.1 mm or 100 mm, package-pin
separations of 0.3 mm or less, packages
with 200 or more pins, surface-mount
packages on both sides of the board, and
multilayer boards

 Boundary-scan test(BST) is a method for testing

boards using a four-wire interface (five wires with
an optional master reset signal).
A good analogy would be theRS-232 interface for
PCs.
The BST standard interface was designed to test
boards, but it is also useful to test ASICs.
The BST interface provides a standard means of
communicating with test circuits on-board an ASIC.
We do need to include extra circuits on an ASIC in
order to use BST.
This is an example of increasing the cost and
complexity (as well as potentially reducing the
performance) of an ASIC to reduce the cost of
testing the ASIC and the system.

boundary scan. (a)Boundary scan is intended to

check for shorts or opens between ICs mounted on
a board. (b)Shorts and opens may also occur inside
the IC package. (c)The boundary-scan architecture
is a long chain of shift registers allowing data to be

Fig (a) illustrates failures that may occur on a PCB

due to shorts or opens in the copper traces on the
board.
Fig (b) Less frequently, failures in the ASIC package
may also arise from shorts and opens in the wire
bonds between the die and the package frame.
Failures in an ASIC package that occur during ASIC
fabrication are caught by the ASIC production
test, but stress during automated handling and
board assembly may cause package failures.
Fig (c)shows how a group of ASICs are linked
together in boundary-scan testing.
To detect the failures (a) or (b) manufacturers use
boundary scan to test every connection between
ASICs on a board

 During boundary scan, test data is loaded into each

ASIC and then driven onto the board traces.
Each ASIC monitors its inputs, captures the data
received, and then shifts the captured data out.
Any defects in the board or ASIC connections will
show up as a discrepancy between expected and
actual measured continuity data.
In order to include BST on an ASIC, we add a special
logic cell to each ASIC I/O pad.
These cells are joined together to form a chain and
create a boundary-scan shift register that extends
around each ASIC.
The input to a boundary-scan shift register is
thetest-data input(TDI).
The output of a boundary-scan shift register is
thetest-data output(TDO).

 These boundary-scan shift registers are then

linked in a serial fashion with the boundaryscan shift registers on other ASICs to form one
long boundary-scan shift register.
The boundary-scan shift register in each ASIC is
one of severaltest-data registers(TDR)
that may be included in each ASIC
A special register that decodes instructions
provides a way to select a particular TDR and
control operation of the boundary-scan test
process.
Controlling all of the operations involved in
selecting registers, loading data, performing a
test, and shifting out results are thetest
clock(TCK) andtest-mode select(TMS).

 Normally the boundary-scan shiftregister cells at each ASIC I/O pad are
transparent, allowing signals to pass
between the I/O pad and the core logic.
When an ASIC is put into boundaryscan test mode, we first tell the TAP
controller which TDR to select.
The TAP controller then tells each
boundary-scan shift register in the
appropriate TDR either to capture input
data, to shift data to the neighbouring
cell, or to output data.

Boundary-scan terminology

BST Cells

A BSC contains two sequential elements.

Thecapture flip-floporcapture registeris
part of a shift register formed by series
connection of BSCs.
Theupdate flip-flop, orupdate latch, is normally
drawn as an edge-triggered D flip-flop, though it may be a
transparent latch.

The inputs to a BSC are:scan in(serial

inorSI);data in(parallel inorPI); and a

 entityDR_cellis port(mode, data_in, shiftDR,

scan_in, clockDR, updateDR: BIT;
data_out, scan_out:outBIT );
endDR_cell;
architecturebehaveofDR_cellis signalq1, q2 :
BIT;begin
CAP :process(clockDR)beginifclockDR = '1'then
ifshiftDR = '0'thenq1 <= data_in;elseq1 <=
scan_in;endif;endif;
endprocess;
UPD :process(updateDR)beginifupdateDR =
'1'thenq2 <= q1;endif;endprocess;
data_out <= data_inwhenmode = '0'elseq2;
scan_out <= q1;
endbehave;

Boundary-Scan Controller

 A boundary-scan controller consists of.

Bypass register.
TDOoutput circuit. The data to be shifted out of
the ASIC onTDOis selected from the serial
outputs of bypass register (BR_SO), instruction
register (IR_SO), or boundary-scan register
(BSR_SO). Notice the registered output means
that data appears onTDOat thenegativeedge
ofTCK. This prevents race conditions between
ASICs.
Instruction register and instruction decoder.
TAP controller.
The BSR (and other optional TDRs) are connected
to the ASIC core logic outside the BST controller.

A Simple Boundary-Scan Example

BSDL(boundary-scan description language)

Theboundary-scan description language(BSDL) is
an extension of IEEE 1149.1 but without any overlap. BSDL
uses a subset of VHDL.
The BSDL for an ASIC is part of an imaginary data sheet; it
is not intended for simulation and does not include models
for any boundary-scan components.
BSDL is a standard way to describe the features and
behavior of an ASIC that includes IEEE 1149.1 boundary
scan and a standard way to pass information to testgeneration software.
Using BSDL, test software can also check that the BST
features are correct.
As an example, test software can use the BSDL to check
that the ASIC uses the correct boundary-scan cells for the
instructions that claim to be supported.
BSDL cannot prove that an implementation works, however.

Faul
ts
Problems may introduce adefectthat in turn
may introduce afault(Sabnis [1990]
describesdefect mechanisms).
Any problem during fabrication may prevent a
transistor from working and may break or join
interconnections
We can measure the overallreliabilityof any
product using themean time between
failures(MTBF) for a repairable product
ormean time to failure(MTTF) for a fatal
failure. We also usefailures in time(FITs)
where 1 FIT equals a single failure in
109hours.

Fault models

Fault is the unwanted disturbance in the result of system

The first column shows thefault levelwhether the fault
occurs in the logic gates on the chip or in the package.
The second column describes thephysical fault
There are several types offault model. First, we simplify
things by mapping from a physical fault to alogical fault.
Next, we distinguish between those logical faults that
degrade the ASIC performance and those faults that are
fatal and stop the ASIC from working at all.
There are three kinds of logical faults: adegradationfault,
anopen-circuitfault, and ashort-circuitfault.
Adegradation faultmay be aparametric
faultordelay fault(timing fault).

 A parametric fault might lead to an incorrect

switching threshold in a TTL/CMOS level
converter at an input, for example.
Adelay faultmight lead to a critical path
being slower than specification.
Delay faults are much harder to test in
production.
Anopen-circuit faultresults from physical
faults such as a bad contact, a piece of
metal that is missing or overetched, or a
break in a polysilicon line.
These physical faults all result in failure to
transmit a logic level from one part of a
circuit to anotheran open circuit.

 Ashort-circuit faultresults from such physical

faults as: underetching of metal; spiking, pinholes
or shorts across the gate oxide; and diffusion
shorts.
These faults result in a circuit being accidentally
connecteda short circuit.
Most short-circuit faults occur in interconnect; often
we call thesebridging faults(BF).
A BF usually results frommetal
coverageproblems that lead to shorts.
You may see reference tofeedback bridging
faultsandnonfeedback bridging faults, a
useful distinction when trying to predict the results
of faults on logic operation.
Bridging faults are a frequent problem in CMOS ICs.

 Physical Faults

F1 is a short between m1 lines

and connects node n1 to VSS.
F2 is an open on the poly layer
and disconnects the gate of
transistor t1 from the rest of the
circuit.
F3 is an open on the poly layer
and disconnects the gate of
transistor t3 from the rest of the
circuit.
F4 is a short on the poly layer
and connects the gate of
transistor t4 to the gate of
transistor t5.
F5 is an open on m1 and
disconnects node n4 from the
output Z1.
F6 is a short on m1 and connects
nodes p5 and p6.
F7 is a nonfatal defect that

Stuck-at Fault Model

Thesingle stuck-at fault(SSF) model assumes
that there is just one fault in the logic we are
testing.
We use a single stuck-at fault model because
amultiple stuck-at fault modelthat could handle
several faults in the logic at the same time is too
complicated to implement
In the SSF model we further assume that the
effect of the physical fault (whatever it may be) is
to create only two kinds of logical fault
The two types of logical faults orstuck-at
faultsare: astuck-at-1 fault(abbreviated toSA1
ors@1) and astuck-at-0 fault(SA0 ors@0).

 We usually inject stuck-at faults to the inputs and

outputs, the pins, of logic cells (AND gates, OR
gates, flip-flops, and so on). We do not inject
faults to the internal nodes of a flip-flop
When a fault changes the circuit behavior, the
change is called thefault effect. Fault effects
travel through the circuit to other logic cells
causing other fault effects. This phenomenon
isfault propagation.
Designers adjust the fault level to the appropriate
level at which they think there may be faults.
Suppose we are performing a fault simulation on
a board and we have already tested the chips.
Then we might set the fault level to the chip level,
placing faults only at the chip pins. For ASICs we
use the logic-cell level.

Logical Faults
(a)Physical faults at the
layout level
(b)We can translate
some of these
faults to the
simplified transistor
schematic.
(c) Only a few of the
physical faults
still remain in a gatelevel fault
model of the logic
cell.
(d)Finally at the
functional-level
fault model of a logic
cell,

 F1 translates to node n1 being stuck at 0, equivalent to A1 being

stuck at 1.
F2 will probably result in node n1 remaining high, equivalent to A1
being stuck at 0.
F3 will affect half of then-channel pull-down stack and may result in
a degradation fault, depending on what happens to the floating gate
of T3. The cell will still work, but the fall time at the output will
approximately double. A fault such as this in the middle of a chain of
logic is extremely hard to detect.
F4 is a bridging fault whose effect depends on the relative strength
of the transistors driving this node. The fault effect is not well
modeled by a stuck-at fault model.
F5 completely disables half of then-channel pulldown stack and will
result in a degradation fault.
F6 shorts the output node to VDD and is equivalent to Z1 stuck at 1.
Fault F7 could result in infant mortality. If this line did break due to
electromigration the cell could no longer pull Z1 up to VDD. This
would translate to a Z1 stuck at 0. This fault would probably be fatal
and stop the ASIC working.

IDDQ
Test
When
they receive a prototype ASIC, experienced

designers measure the resistance between VDD and

GND pins.
Providing there is not a short between VDD and
GND, they connect the power supplies and measure
the power-supply current.
From experience they know that a supply current of
more than a few milliamperes indicates a bad chip.
This is exactly what we want in production test: Find
the bad chips quickly, get them off the tester, and
save expensive tester time.
AnIDDQ(IDDstands for the supply current, and Q
stands for quiescent) test is one of the first
production tests applied to a chip on the tester,
after the chip logic has been initialized

Fault Simulation

We usefault simulationafter we have

completed logic simulation to see what
happens in a design when we
deliberately introduce faults.
In a production test we only have
access to the package pins
theprimary inputs(PIs) andprimary
outputs(POs).
To test an ASIC we must devise a series
of sets of input patterns that will detect
any faults