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ARM7,ARM9,ARM11 Processors
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ARM processors versions

ARM7, ARM9 & ARM11 features, advantages &
suitability in embedded application
ARM7 : data flow model
programmers model
modes of operations
Instruction set
programming in assembly language
Reference Book: ARM System Developers Guide, Andrew Sloss
For understanding LPC 2148 read book, The Insiders Guide to the Philips ARM7
based Controllers.

ARM history
3

1983 developed by Acorn computers

To

replace 6502 in BBC computers

4-men VLSI design team
It simplicity came from the inexperience team
Match the needs for generalized SoC for reasonable power, performance
and die size

By 1985, design of first commercial RISC machine called

Acron RISC Machine (ARM).
In 1990, there were 12 engineers and 1 CEO, with no
customers and a little money.
1990 ARM (Advanced RISC Machine), owned by Acorn,
Apple and VLSI
In 1990s TI incorporated ARM for mobile phones
By 1998 there were 13 millionaires in company.

Why ARM?
4

One of the most licensed and thus widespread processor cores

in the world
Used in PDA (Personal Digital Assistant), cell phones,
multimedia players, handheld game console, digital TV and
cameras

ARM7: GBA , iPod

ARM9: NDS , PSP (Play Station Portable), Sony Ericsson, BenQ
ARM11: Apple iPhone, Nokia N93, N800
75% of 32-bit embedded processors

Used especially in portable devices due to its low power

consumption and reasonable performance

ARM processors
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A simple but powerful design

A whole family of designs sharing similar design principles
and a common instruction set

Naming ARM
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ARMxyzTDMIEJFS
x: series - 7/9/11/cortex
y: MMU
z: cache
T: Thumb 16 bit instruction set
D: On chip Debug support
M: Enhanced Multiplier
I: Embedded ICE (built-in debugger hardware-)
E: Enhanced instruction
J: Jazelle (JVM): - 8 bit mode
F: Floating-point
S: Synthesizable version (source code version for EDA tools)

ARM Processor Versions

7

7/50

Development of the ARM Architecture

8

v4
Halfword and
signed halfword /
byte support
System mode
Thumb
instruction set
(v4T)

v5
Improved
interworking
Saturated arithmetic
DSP - MAC
instructions
Extensions:
Jazelle (5TEJ)

v6
SIMD Instructions
Multi-processing
v6 Memory architecture
Unaligned data support
Extensions:
Thumb-2 (6T2)
TrustZone (6Z)
Multicore (6K)
Thumb only (6-M)

v7
Thumb-2
Architecture Profiles

7-A
Applications
7-R - Real-time
7-M - Microcontroller

Note that implementations of the same architecture can be

different
Cortex-A8 - architecture v7-A, with a 13-stage pipeline
Cortex-A9 - architecture v7-A, with an 8-stage pipeline

ARM7 - Features
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32-bit RISC processor (32-bit data & address bus)

Big and Little Endian operating modes
High performance RISC (17 MIPS sustained @ 25 MHz (25
MIPS peak) @ 3V)
Low power consumption (0.6mA/MHz @ 3V fabricated in .
8m CMOS)
Fully static operation (ideal for power-sensitive applications)
Fast interrupt response (for real-time applications)
Virtual Memory System Support
Excellent high-level language support
Simple but powerful instruction set

ARM7 - Applications
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The ARM7 is ideally suited to those applications requiring

RISC performance from a compact, power-efficient
processor
Telecomms - GSM terminal controller
Datacomms - Protocol conversion
Portable Computing - Palmtop computer
Portable Instrument - Hendheld data acquisition unit
Automotive - Engine management unit
Information systems - Smart cards
Imaging - JPEG controller

ARM9 - Features
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Some of the features offered by the ARM9 processor are:

Java acceleration
DSP extensions
Optional floating point unit
Flexible local memory system with cache and exceptional
Tightly Coupled Memory (TCM) integration
Binary compatibility with the ARM7TDMI processor

ARM9 - Applications
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Product Type

Application

Consumer

Smartphones, PDA, Set top box,

Electronic toys, Digital still cameras,
Digital video cameras etc

Networking

Wireless LAN, 802.11, Bluetooth,

Firewire, SCSI, 2.5G/3G Baseband etc

Automotive

Power train, ABS, Body systems,

Navigation, Infotainment etc

Embedded

USB controllers,bluetooth controllers,

medical scanners etc

Storage

HDD controllers, solid state drives etc

ARM11 - Features
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Powerful ARMv6 instruction set architecture.

ARM Thumb instruction set reduces memory bandwidth and size
requirements by up to 35%.
ARM Jazelle technology for efficient embedded Java execution.
ARM DSP extensions SIMD (Single Instruction Multiple Data)
media processing extensions deliver up to 2x performance for
video processing.
ARM TrustZone technology for on-chip security foundation.

ARM11 - Features
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ARM1176JZ-S and ARM1176JZF-S processors Thumb-2

technology (ARM1156(F)-S only) for enhanced performance,
energy efficiency and code density, Low power consumption:
0.21 mW/MHz (65G) including cache controllers.
Energy saving power-down modes in advanced processes.
High performance integer processor 8-stage integer pipeline
delivers high clock frequency (9 stages for ARM1156T2(F)-S).
Separate load-store and arithmetic pipelines.
Branch Prediction and Return Stack.

ARM11 - Applications
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Consumer:- Smart Phone, Home Video Security

Automotive :-Electronic Control unit of automobiles

What is RISC?
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RISC is an acronym for Reduced Instruction Set Computers

An opponent of the RISC processor is CISC which is
Complex Instruction Set Computers.
Goals of these 2 are to improve system performance.

What is RISC?...
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CISC and RISC differ in complexities of their instruction sets

where CISC is more complex than RISC.

The reduced number and complexity of instructions of the

instruction sets of RISC processors are the basis for the
improved performance.

For example, the smaller instruction set allows a designer to

implement a hardwired control unit which runs at a higher
clock rate than its equivalent micro sequenced control unit.

18

Traditional Complex Instruction Set Computer (CISC) relies

more on the hardware for instruction functionality, and
consequently the CISC instructions are more Complicated

The RISC Design Philosophy

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Aimed at delivering simple but powerful instructions that execute within

a single cycle at a high clock speed.
Concentrates on reducing the complexity of instructions performed by
the hardware to provide greater flexibility and intelligence in software
rather than hardware.
A RISC design places greater demands on the compiler.

The RISC Philosophy

(four major design rules)
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1. Instructions
Reduced number of instruction classes to provide simple
operations that can each execute in a single cycle.
Each instruction is a fixed length to allow the pipeline to
fetch future instructions before decoding the current
instruction. (Unlike CISC)
2. Pipelines
The processing of instructions is broken down into smaller
units that can be executed in parallel by pipelines.
Ideally the pipeline advances by one step on each cycle for
maximum
throughput. Instructions can be decoded in
one pipeline stage.

The RISC Philosophy

(four major design rules)
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3. Registers
RISC machines have a large general-purpose register set.
Any register can contain either data or an address.
Registers act as the fast local memory store for all data
processing

operations.

(CISC processors: Have dedicated registers for specific

purposes)

The RISC Philosophy

(four major design rules)
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4. Load-Store Architecture
The processor operates on data held in registers.
Separate load and store instructions : transfer data between
the register bank and external memory.
Memory accesses are costly, so separating memory accesses
from data processing provides an advantage that use of data
items held in the register bank multiple times without needing
multiple memory accesses.
(CISC design : The data processing operations can act on
memory directly)

ARM Fundamentals
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A key component of many successful 32-bit

embedded systems
First ARM1 prototype in 1985
One of ARMs most successful cores is the
ARM7-TDMI

TDMI

(Thumb instruction,

Debugger,

Multiplier, ICE)

known for its high code density and

low
consumption

power

The ARM Design Philosophy

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Physical features of the ARM processor :

Portable embedded systems require
1.Some form of battery power
( Applications such as mobile phones and personal digital assistants
(PDAs))
The ARM processor has been specifically designed to be small to reduce
power consumption and extend battery operation
2. High code density
(Mobile phones have limited memory :cost and/or physical size restrictions)
High code density : useful for applications that have limited on-board
memory.
3. Price sensitive and use of slow and low-cost memory devices
(Digital cameras: require high volume)

The ARM Design Philosophy

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4. Reduced die area (for embedded processor: a single-chip solution)

Embedded processor: Smaller area used by the Specialized peripherals.
This in turn reduces the cost of the design and manufacturing since fewer
discrete chips are required for the end product.
5. Debug capability
ARM : Hardware debug technology within the processor
(view of --what is happening while the processor is executing
code?)
Has a direct effect on the time to market and reduces overall development
costs.

The ARM Design Philosophy

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6. Constraints of the Embedded System.

Performance Measure in todays systems : Total effective
system performance and power consumption (& not raw
processor speed)

The ARM Processor

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Controls the embedded device.

Different versions of the ARM processor are available to suit the desired
operating characteristics.
An ARM Processor
1. Core
(the execution engine that processes instructions and manipulates data)
+
2. Surrounding Components
( that interface it with a bus & include memory management and caches)

The ARM Processor

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3. Controllers : Coordinate important functional blocks of the

system
Two commonly found controllers:
Interrupt and memory controllers
4. The Peripherals :
Provide all the input-output capability external to the
chip and are responsible for the uniqueness of the embedded
device.
5. Bus :
Used to communicate between different parts of the
device

ARM Processor Dataflow Model

An ARM Core = Functional units connected by data buses
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Algorithm of the ARM Processor Core Operation

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1.

Data (instruction to execute or a data item ) enters the processor core

through the Data bus. Data items and instructions share the same bus.

2. The instruction decoder translates instructions before they are executed.

The ARM processor : uses a load-store architecture & has two instruction
types for transferring data in and out of the processor.
a. Load instructions copy data from memory to registers in the core, and
b. Store instructions copy data from registers to memory.
c. No data processing instructions that directly manipulate data in memory.
3.

Data processing is carried out solely in registers.

Algorithm of the ARM Processor Core Operation

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4.

Data items are placed in the register filea storage bank

made up of 32-bit registers. Most instructions treat the
registers as holding signed or unsigned 32-bit values. The
sign extend hardware converts signed 8-bit and 16-bit
numbers to 32-bit values as they are read from memory
and placed in a register.

5. ARM instructions typically have two source registers, Rn

and Rm, and a single result or destination register, Rd.

Algorithm of the ARM Processor Core Operation

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6. Source operands are read from the register file using the
internal buses A and B, respectively.
7. The ALU (arithmetic logic unit) or MAC (multiplyaccumulate unit) takes the register values Rn and Rm
from the A and B buses and computes a result.
8. Data processing instructions write the result in Rd directly
to the register file.
9. Load and store instructions use the ALU to generate an
address to be held in the address register and broadcast on
the Address bus.

Algorithm of the ARM Processor Core Operation

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10. Register Rm alternatively can be preprocessed in the

barrel shifter before it enters the ALU. Together the
barrel shifter and ALU can calculate a wide range of
expressions and addresses.
11. After passing through the functional units, the result in
Rd is written back to the register file using the Result
bus.
12. For load and store instructions the incrementer updates
the address register before the core reads or writes the
next register value from or to the next sequential
memory location.

Programmers Model
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It contains the following :

Registers
Processor operating states
Operating modes
Memory formats
Data types
The program status registers
Exceptions
Interrupt latencies
Reset

Registers
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They are of two typesGeneral purpose

Special Purpose

The ARM7TDMI processor has a total of 37

registers:
31 general-purpose 32-bit registers
6 status registers.
These registers are not all accessible at the same time

Registers
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General Purpose Registers

1. Hold either data or an address.
2. Identified with the letter r prefixed to the register number. (register 4 = r4).
3. All the registers are 32 bits in size.
4. Up to 18 active registers: 16 data registers and 2 processor status registers.
5. Data registers are visible to the programmer (r0 to r15).
6. Three special function registers : r13, r14, and r15. They are frequently given
different labels to differentiate them from the other registers.
Register r13 = Stack Pointer (sp) : stores the head of the stack in the
current processor mode.
Register r14 = Link register (lr) : whenever the core calls a
subroutine, it puts the return address in this register.
Register r15=Program Counter (pc): contains the address of the next
instruction to be fetched by the processor.
Registers r13 and r14 can also be used as general-purpose registers

Registers
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7. Registers r0 to r13 are orthogonalany instruction that

you can apply to r0 you can equally well apply to any of the
other registers.
8. There are instructions that treat r14 and r15 in a special
way.
9. The register file contains all the registers available to a
programmer. Which registers are visible to the programmer
depend upon the current mode of the processor.
Program Status Registers
cpsr and spsr
(the current and saved program status registers)

38

Unbanked Registers
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r0 to r7 are unbanked registers- Means in all processing modes

they are representing same 32 bit physical register.
They are completely general-purpose registers.
No special use.

Banked Registers (r8 to r14)

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20 registers are hidden from a program at different times. These

registers are called banked registers
They are available only when the processor is in a particular
mode
For example, abort mode has banked registers r13_abt, r14_abt
and spsr_abt.

Banked Registers & States

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Banked Registers
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All processor modes except system mode have a set of

associated banked registers
If you change processor mode, a banked register from
the new mode will replace an existing register.
For example, when the processor is in the interrupt
request mode, the instructions you execute still access
registers named r13 and r14. However, these registers are
the banked registers r13_irq and r14_irq.
The user mode registers r13_usr and r14_usr are not
affected by the instruction referencing these registers.

Banked Registers
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The processor mode can be changed by

1.A program that writes directly to the cpsr
2.Hardware when the core responds to an exception or
interrupt
The following exceptions and interrupts cause a mode
change:
Reset
Interrupt request
Fast interrupt request
Software interrupt
Data abort
Prefetch abort,
Undefined instruction

Banked Registers
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Figure illustrates what happens when an interrupt forces a

mode change.

Banked Registers
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User registers r13 and r14 to be banked

The user registers are replaced with registers r13_irq
and r14_irq
Respectively r14_irq contains the return address and
r13_irq contains the stack pointer for interrupt reques
mode.
The saved program status register (spsr), stores the
previous modes cpsr.

Banked Registers
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To return back to user mode, a special return instruction

is used that instructs the core to restore the original cpsr
from the spsr_irq and bank in the user registers r13 and
r14.
Another important feature to note is that the cpsr is not
copied into the spsr when a mode change is forced due to
a program writing directly to the cpsr.
The saving of the cpsr only occurs when an exception or
interrupt is raised

47

Basic Layout of a Generic Program Status Register

Four fields ( each 8 bits wide)
flags, status, extension, and control
Control field : the processor mode, state, and interrupt mask bits.
Flags field : the condition flags.
Shaded parts: Reserved for future expansion.
[ Some ARM processor cores have extra bits allocated. For example, the J
bit, which can be found in the flags field, is only available on
Jazelle-enabled processors]

Current Program Status Register (Bits 0-4)

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Current Program Status Register(Bit 5)

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T bit
The T bit reflects the operating state:
when the T bit is set, the processor is executing in
Thumb state
when the T bit is clear, the processor executing
in ARM state.

Current Program Status Register (Bits 6-7)

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Interrupt Masks
Interrupt masks are used to stop specific interrupt requests
from interrupting the processor
The I and F bits are the interrupt disable bits:
when the I bit is set, IRQ interrupts are disabled
when the F bit is set, FIQ interrupts are disabled

Current Program Status Register (Bits 27-31)

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Condition Flags
Condition flags are updated by comparisons and the result
of ALU operations that specify the S instruction suffix.

Current Program Status Register

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With processor cores that include the DSP extensions,

the Q bit indicates if an overflow or saturation has
occurred in an enhanced DSP instruction
The flag is sticky in the sense that the hardware only
sets this flag.
To clear the flag you need to write to the cpsr directly.

Processor Modes
Determines
1. which registers are active and
2. the access rights to the cpsr register itself
53

Processor modes
1.Privileged
2.non-privileged
Privileged mode : Allows full read-write access to the cpsr
Non-privileged mode: allows only read operation access to the
control field in the cpsr but still allows read-write access to the
condition flags.

Seven Processor Modes

Six privileged modes
(abort, fast interrupt request, interrupt request, supervisor, system,
undefined)
One Non-privileged mode
(user)

Pipeline
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Mechanism a RISC processor to execute instructions

Speeds up execution by fetching the next instruction while
other instructions are being decoded and executed
Allows the core to execute an instruction every cycle

55

Fetch :

Loads an instruction from memory

Decode: Identifies the instruction to be executed
Execute : Processes the instruction and writes the result
back to a register.

As the pipeline length increases, the amount of work

done at each stage is reduced, which allows the processor to
attain a higher operating frequency.

System latency also increases because it takes more

cycles to fill the pipeline before the core can execute an
instruction.

The Thumb-state register set

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The Thumb-state register set is a subset of the ARM-state

set. The programmer has access to:
8 general registers, r0r7
the PC
the SP
the LR
the CPSR.

The Thumb-state register set

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The relationship between ARM-state

and Thumb-state registers
58

Operating modes
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The ARM7TDMI processor has seven modes of operation:

User mode is the usual ARM program execution state, and is
used for executing most application programs.
Fast Interrupt (FIQ) mode supports a data transfer or channel
process.
Interrupt (IRQ) mode is used for general-purpose interrupt
handling.
Supervisor mode is a protected mode for the operating
system.

Operating modes
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Abort mode is entered after a data or instruction

Prefetch Abort.
System mode is a privileged user mode for the operating
system.
Undefined mode is entered when an undefined
instruction is executed.
Note
You can only enter System mode from another privileged
mode by modifying the mode bit of the Current Program
Status Register (CPSR).

Processor operating states

61

The ARM7TDMI processor has two operating states:

ARM
32-bit, word-aligned ARM instructions are
executed in this state.
Thumb 16-bit, halfword-aligned Thumb instructions
are executed in this state.

Processor operating states

62

Switching state
The operating state of the ARM7TDMI core can be
switched between ARM state and Thumb state using
the BX instruction.
All exception handling is entered in ARM state. If
an exception occurs in Thumb state, the processor
reverts to ARM state.
The transition back to Thumb state occurs automatically
on return.
An exception handler can change to Thumb state but
it must return to ARM state to allow the exception handler
to terminate correctly

Memory formats
63

The ARM7TDMI processor views memory as a linear

collection of bytes numbered in ascending order from
zero.
For example:
bytes zero to three hold the first stored word
bytes four to seven hold the second stored word.
The ARM7TDMI processor is bi-endian and can treat
words in memory as being stored in either:
Little-endian.
Big-Endian

Memory formats
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Little-endian

Memory formats
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Big-Endian

Data types
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The ARM7TDMI processor supports the following data types:

words, 32-bit
half words, 16-bit
bytes, 8-bit.
You must align these as follows:
word quantities must be aligned to four-byte boundaries
half-word quantities must be aligned to two-byte boundaries
byte quantities can be placed on any byte boundary.

Exceptions
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Exceptions arise whenever the normal flow of a program

has to be halted temporarily, for example, to service an
interrupt from a peripheral.
Before attempting to handle an exception, the
ARM7TDMI processor preserves the current processor
state so that the original program can resume when the
handler routine has finished

Exceptions
68

Entering an exception
1. Preserves the address of the next instruction in the
appropriate LR.
When the exception entry is from ARM state, the
ARM7TDMI processor copies the address of the next
instruction into the LR, current PC+4 or PC+8 depending
on the exception.
When the exception entry is from Thumb state, the
ARM7TDMI processor writes the value of the PC into
the LR, offset by a value, current PC+4 or PC+8
depending on the exception, that causes the program to
resume from the correct place on return.

Exceptions
69

Entering an exception
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on
the exception.
4. Forces the PC to fetch the next instruction from the
relevant exception vector.

Exceptions
Leaving an exception
70

When an exception is completed, the exception handler must:

1.Move the LR, minus an offset to the PC. The offset varies
according to the type of exception,

1.Copy the SPSR back to the CPSR.

2.Clear the interrupt disable flags that were set on entry.

Exceptions
Fast Interrupt Request
71

The Fast Interrupt Request (FIQ) exception supports data

transfers or channel processes.
An FIQ is externally generated by taking the nFIQ input LOW.
The input passes into the core through a synchronizer.
Irrespective of whether exception entry is from ARM state or
from Thumb state, an FIQ handler returns from the interrupt by
executing:
SUBS PC,R14_fiq,#4
FIQ exceptions can be disabled within a privileged mode by
setting the CPSR F flag. When the F flag is clear, the
ARM7TDMI processor checks for a LOW level on the
output of the FIQ synchronizer at the end of each instruction.

Exceptions
Interrupt Request
72

The Interrupt Request (IRQ) exception is a normal interrupt

caused by a LOW level on the nIRQ input. IRQ has a lower
priority than FIQ, and is masked on entry to an FIQ
sequence. Also nIRQ passes into the core through a
synchronizer.
Irrespective of whether exception entry is from ARM state or
Thumb state, an IRQ handler returns from the interrupt by
executing:
SUBS PC,R14_irq,#4
You can disable IRQ at any time, by setting the I bit in the
CPSR from a privileged
mode.

Exceptions
Abort
73

An abort indicates that the current memory access cannot be

completed. It is signaled by the external ABORT input.
The ARM7TDMI-S checks for the abort exception at the end of
memory access cycles.
There are two types of abort:
A Prefetch Abort occurs during an instruction prefetch.
A Data Abort occurs during a data access.

Exceptions
Prefetch Abort
74

When a Prefetch Abort occurs, the ARM7TDMI-S core marks

the prefetched instruction as invalid,
but does not take the exception until the instruction reaches the
execute stage of the pipeline.
If the instruction is not executed because a branch occurs while
it is in the pipeline, the abort does not take place.
SUBS PC,R14_abt,#4 Following instruction

Exceptions
Data Abort
75

When a Data Abort occurs, the action taken

depends on the instruction type.

Exceptions
Data Abort
76

When a Data Abort occurs, the action taken depends on

the instruction type.
After fixing the reason for the abort, the handler must
execute the following return instruction irrespective of
the processor operating state at the point of entry:
SUBS PC,R14_abt,#8

Exceptions
Software interrupt instruction
77

The Software Interrupt (SWI) is used to enter Supervisor mode,

usually to request a particular supervisor function.
A SWI handler returns by executing the following instruction
irrespective of the processor operating state:
MOVS PC, R14_svc
This action restores the PC and CPSR, and returns to the
instruction following the SWI.

Exceptions
Undefined instruction
78

When the ARM7TDMI-S processor encounters an instruction

neither belongs to it not to coprocessor, the ARM7TDMI-S core
takes the undefined instruction trap.
Software can use this mechanism to extend the ARM instruction
set by emulating undefined coprocessor instructions.
MOVS PC,R14_und
This action restores the CPSR and returns to the next instruction after the
undefined instruction.

Priorities of Exceptions
79

1. Reset (highest priority).

2. Data Abort.
3. FIQ.
4. IRQ.
5. Prefetch Abort.
6. Undefined instruction.
7. SWI (lowest priority)-Software Interruptmode, usually to request a particular supervisor function.

is used to enter Supervisor

Exceptions
Exception entry and exit summary
80

Exceptions
Exception vectors
81

In this table, I and F represent the previous value of the

IRQ and FIQ interrupt disable bits respectively in the
CPSR.

Exceptions
Exception vectors
82

Exceptions
83

Some exceptions cannot occur together:

The undefined instruction and SWI exceptions are mutually
exclusive. Each corresponds to a particular, non-overlapping,
decoding of the current instruction.
When FIQs are enabled, and a Data Abort occurs at the same
time as an FIQ, the ARM7TDMI processor enters the Data Abort
handler, and proceeds immediately to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to
resume execution.
Data Aborts must have higher priority than FIQs to ensure that the
transfer error does not escape detection.

Interrupt latencies
84

Maximum interrupt latencies

When FIQs are enabled, the worst-case latency for FIQ
comprises a combination of:
The longest time the request can take to pass through the
synchronizer, Tsyncmax (four processor cycles).
The time for the longest instruction to complete, Tldm. The
longest instruction, is an LDM which loads all the registers
including the PC. Tldm is 20 cycles in a zero wait state system.
The time for the Data Abort entry, Texc (three cycles).
The time for FIQ entry, Tfiq (two cycles)

Interrupt latencies
85

Maximum interrupt latencies

The total latency is therefore 29 processor cycles, just over 0.7
microseconds in a 40MHz system. At the end of this time, the
ARM7TDMI processor executes the instruction at 0x1c.
The maximum IRQ latency calculation is similar, but must allow
for the fact that FIQ, having higher priority, can delay entry into
the IRQ handling routine for an arbitrary length of time.

Interrupt latencies
86

Minimum interrupt latencies

The minimum latency for FIQ or IRQ is the shortest time

the request can take through the synchronizer, Tsyncmin,
plus Tfiq, a total of five processor cycles.

Reset
87

When the nRESET signal goes LOW a reset occurs, and

the ARM7TDMI core abandons the executing instruction
and continues to increment the address bus as if still
fetching word or halfword instructions. nMREQ and SEQ
indicates internal cycles during this time

Reset
88

When nRESET goes HIGH again, the ARM7TDMI processor:

1. Overwrites R14_svc and SPSR_svc by copying the current
values of the PC and CPSR into them. The values of the PC and
CPSR are indeterminate.
2. Forces M[4:0] to b10011, Supervisor mode, sets the I and F
bits, and clears the T-bit in the CPSR.
3. Forces the PC to fetch the next instruction from address 0x00.
4. Reverts to ARM state if necessary and resumes execution.
After reset, all register values except the PC and CPSR are
indeterminate.