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UNIT II
ARM7 BASED MICROCONTROLLER
ARM7 Based Microcontroller LPC2148:
Features
Architecture (Block Diagram and Its Description)
System Control Block (PLL and VPB divider)
Memory Map
GPIO
Pin Connect Block
Timer
Interfacing with LED, LCD, GLCD, KEYPAD

ARM7 Based Microcontroller LPC2148:


Features
2

16/32-bit ARM7TDMI-S microcontroller- LQFP64 package


8 to 40 kB of on-chip static RAM
32 to 512 kB of on-chip flash program memory
128 bit wide interface/accelerator enables high speed 60 MHz
operation
In-System/In-Application Programming (ISP/IAP) via on-chip
boot-loader software
Single flash sector or full chip erase in 400 ms and programming
of 256 bytes in 1 ms
Embedded ICE RT and Embedded Trace interfaces- Real-time
debugging & and high speed tracing of instruction execution

Features
3

USB 2.0 Full Speed compliant Device Controller with 2 kB of


endpoint RAM. In addition, the LPC2146/8 provide 8 kB of
on-chip RAM accessible to USB by DMA
One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D
converters provide a total of 6/14 analog inputs, with
conversion times as low as 2.44 s per channel
Single 10-bit D/A converter provides variable analog output
Two 32-bit timers/external event counters (with four capture
and four compare channels each), PWM unit (six outputs) and
watchdog
Low power RTC with independent power and dedicated 32
kHz clock input

Features
4

Serial interfaces

Two UARTs (16C550),


Two Fast I2C-bus (400 kbit/s),
SPI and SSP (Synchronous Serial Port) with buffering and variable
data length capabilities.

Vectored interrupt controller


Up to 45 of 5 V tolerant fast general purpose I/O pins in a LQFP64
package
Up to nine edge or level sensitive external interrupt pins available
60 MHz maximum CPU clock available from programmable onchip PLL with settling time of 100 s.

Features
5

On-chip oscillator: External crystal 1 MHz to 30 MHz,


External oscillator: up to 50 MHz.
Power saving modes: Idle and Power-down
Additional power optimization:

Individual enable/disable of peripheral functions


Peripheral clock scaling.

Processor wake-up from Power-down mode via external


interrupt, USB, Brown-Out Detect (BOD) or Real-Time Clock
(RTC)
Single power supply chip with Power-On Reset (POR) and
BOD circuits: CPU operating voltage range of 3.0 V to 3.6 V
(3.3 V 10 %) with 5 V tolerant I/O pads.

ARM7 Based
Microcontroller LPC2148:
6

Architecture

(1) Pins shared with GPIO.


(2) LPCC2144/6/8 only.
(3) USB DMA
controller with 8 kB of
RAM accessible as
general purpose RAM
and/or DMA is
available in LPC2146/8
only.
(4) LPC2142/4/6/8 only.

Architecture
7

The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with


emulation support
The ARM7 Local Bus for interface to on-chip memory
controllers
The AMBA (Advanced Microcontroller Bus Architecture)
Advanced High-performance Bus (AHB) for interface to the
interrupt controller
The APB (ARM Peripheral Bus) for connection to on-chip
peripheral functions
ARM7TDMI-S processor configured in little-endian byte order
The connection of on-chip peripherals to device pins is
controlled by a Pin Connect Block

Architecture
8

AHB peripherals are allocated a 2 megabyte range of addresses


at the very top of the 4 gigabyte ARM memory space
Each AHB peripheral is allocated a 16 kB address space within
the AHB address space
LPC2141/2/4/6/8 peripheral functions (other than interrupt
controller) are connected to the APB bus
The AHB to APB bridge interfaces the APB bus to the AHB
bus
APB peripherals are also allocated a 2 megabyte range of
addresses, beginning at the 3.5 gigabyte address point
Each APB peripheral is allocated a 16 kB address space within
the APB address space

Architecture
9

ARM7TDMI-S processor:
The ARM7TDMI-S is a general purpose 32-bit
microprocessor, which offers high performance and very low
power consumption

Reduced Instruction Set Computer (RISC)

High instruction throughput and impressive real-time interrupt


response from a small and,

Cost-effective processor core.

Architecture
10

Pipeline techniques are employed so that all parts of the


processing and memory systems can operate continuously
The ARM7TDMI-S: THUMB, which makes it ideally suited
to high-volume applications with memory restrictions, or
applications where code density is an issue
The key idea behind THUMB is that of a super-reduced
instruction set
The THUMB allows to approach twice the density of standard
ARM code while retaining most of the ARMs performance
advantage

Architecture
11

On-chip flash memory system:


The LPC21418 incorporate a 512 kB Flash memory system.
This memory may be used for both code and data storage
Programming of the Flash memory: several ways:

over the serial built-in JTAG interface,


using In System Programming (ISP) and UART0,
or by means of In Application Programming (IAP) capabilities.

When the LPC2141/2/4/6/8 on-chip bootloader is used, 32 kB,


64 kB, 128 kB, 256 kB, and 500 kB of Flash memory is
available for user code
The LPC2141/2/4/6/8 Flash memory provides minimum of
100,000 erase/write cycles and 20 years of data-retention

Architecture
12

On-chip Static RAM (SRAM):


On-chip Static RAM (SRAM): Code and/or data storage
The on-chip SRAM: as 8-bits, 16-bits, and 32-bits
The LPC2141/2/4/6/8 provide 8/16/32 kB of static RAM,
respectively
The LPC2141/2/4/6/8 SRAM: byte-addressed memory
Word and half-word accesses to the memory ignore the
alignment of the address and access the naturally-aligned
value that is addressed

Architecture
13

This rule applies to both off and on-chip memory usage.

The SRAM controller incorporates a write-back buffer in


order to prevent CPU stalls during back-to-back writes.
The write-back buffer always holds the last data sent by
software to the SRAM.
This data is only written to the SRAM when another write is
requested by software

Architecture
14

If a chip reset occurs, actual SRAM contents will not reflect


the most recent write request
Two identical writes to a location guarantee that the data will
be present after a Reset.
Alternatively, a dummy write operation before entering idle or
power-down mode will similarly guarantee that the last data
written will be present in SRAM after a subsequent reset

ARM7 Based
Microcontroller
LPC2148:
15

Memory maps

Memory maps
16

Both the AHB and APB peripheral areas are 2 megabyte


spaces which are divided up into 128 peripherals
Each peripheral space is 16 kilobytes in size
All peripheral register addresses are word aligned (to 32-bit
boundaries) regardless of their size. This eliminates the need
for byte lane mapping hardware that would be required to
allow byte (8-bit) or half-word (16-bit) accesses to occur at
smaller boundaries An implication of this is that word and
half-word registers must be accessed all at once. For example,
it is not possible to read or write the upper byte of a word
register separately

Memory maps
17

Memory maps
18

Memory maps
19

Both the AHB and APB peripheral areas are 2 megabyte


spaces which are divided up into 128 peripherals
Each peripheral space is 16 kilobytes in size
All peripheral register addresses are word aligned (to 32-bit
boundaries) regardless of their size. This eliminates the need
for byte lane mapping hardware that would be required to
allow byte (8-bit) or half-word (16-bit) accesses to occur at
smaller boundaries An implication of this is that word and
half-word registers must be accessed all at once. For example,
it is not possible to read or write the upper byte of a word
register separately

AHB Peripherals
20

ARM7 Based Microcontroller LPC2148:


system control block functions
21

The System Control Block includes several system features and


control registers for a number of functions. Not related to
specific peripheral devices. These include:
Crystal

Oscillator
External Interrupt Inputs
Miscellaneous System Controls and Status
Memory Mapping Control
PLL
Power Control
Reset
APB Divider
Wakeup Timer

system control block functions


22

Phase Locked Loop (PLL)


There are two PLL modules in the LPC2141/2/4/6/8
microcontroller.
The PLL0 is used to generate the CCLK clock (system clock)
the PLL1 has to supply the clock for the USB at the fixed rate
of 48 MHz.
Structurally these two PLLs are identical with exception of
the PLL interrupt capabilities reserved only for the PLL0.

system control block functions


PLL
23

The PLL0 and PLL1- Input clock frequency range 10-25 MHz
only.
The input frequency is multiplied: 10 MHz to 60 MHz for the
CCLK and 48 MHz for the USB clock using a Current
Controlled Oscillators (CCO).
The multiplier can be an integer value from 1 to 32
The CCO range- 156 MHz to 320 MHz, so there is an
additional divider in the loop to keep the CCO within its
frequency range while the PLL is providing the desired output
frequency.

system control block functions


PLL
24

The output divider may be set to divide by 2, 4, 8, or 16 to


produce the output clock.
Since the minimum output divider value is 2, it is insured that
the PLL output has a 50% duty cycle.
PLL activation is controlled via the PLLCON register.
The PLL multiplier and divider values are controlled by the
PLLCFG register.
These two registers are protected in order to prevent
accidental alteration of PLL parameters or deactivation of the
PLL.

system control block functions


PLL
25

Since all chip operations, including the Watchdog Timer, are


dependent on the PLL0 when it is providing the chip clock,
accidental changes to the PLL setup could result in
unexpected behavior of the microcontroller
The same concern is present with the PLL1 and the USB
Both PLLs are turned off and bypassed following a chip Reset
and when by entering Power-down mode.
The PLL is enabled by software only.
The program must configure and activate the PLL, wait for
the PLL to Lock, then connect to the PLL as a clock source

system control block functions


PLL
26

system control block functions


PLL
27

PLL Control register (PLL0CON - 0xE01F C080,


PLL1CON - 0xE01F C0A0)
28

The PLLCON register contains the bits that enable


and connect the PLL.
Enabling the PLL allows it to attempt to lock to the
current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all
chip functions to run from the PLL output clock.
Changes to the PLLCON register do not take effect
until a correct PLL feed sequence has been given

PLL Control register: (PLL0CON - address 0xE01F C080,


PLL1CON address 0xE01F C0A0) bit description
29

PLL Configuration register (PLL0CFG - 0xE01F C084,


PLL1CFG - 0xE01F C0A4)
30

The PLLCFG register contains the PLL multiplier


and divider values.
Changes to the PLLCFG register do not take effect
until a correct PLL feed sequence has been given

PLL Configuration register (PLL0CFG - address 0xE01F C084,


PLL1CFG address 0xE01F C0A4) bit description
31

PLL Status register (PLL0STAT - 0xE01F C088,


PLL1STAT - 0xE01F C0A8)
32

The read-only PLLSTAT register provides the


actual PLL parameters that are in effect at the time
it is read, as well as the PLL status.
PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those
registers do not take effect until a proper PLL feed
has occurred

33

PLL Status register (PLL0STAT - address 0xE01F


C088, PLL1STAT address 0xE01F C0A8) bit
description

PLL Interrupt
34

The PLOCK bit in the PLLSTAT register is


connected to the interrupt controller.
This allows for software to turn on the PLL and
continue with other functions without having to
wait for the PLL to achieve lock.
When the interrupt occurs (PLOCK = 1), the PLL
may be connected, and the interrupt disabled.

35

PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED - 0xE01F C0AC)


36

A correct feed sequence must be written to the


PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect.
The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence,
and must be consecutive APB bus cycles.

PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED - 0xE01F C0AC)


37

The latter requirement implies that interrupts must


be disabled for the duration of the PLL feed
operation.
If either of the feed values is incorrect, or one of
the previously mentioned conditions is not met, any
changes to the PLLCON or PLLCFG register will
not become effective.

system control block functions


PLL
38

Example 1: an application not using the USB - configuring the PLL0


System design asks for FOSC= 10 MHz and requires CCLK = 60 MHz.
Based on these specifications,
M = CCLK / Fosc = 60 MHz / 10 MHz = 6.
Consequently, M - 1 = 5 will be written as PLLCFG[4:0].
Value for P can be derived from P = FCCO / (CCLK x 2),
using condition that FCCO must be in range of 156 MHz to 320 MHz.
Assuming the lowest allowed frequency for FCCO = 156 MHz,
P = 156 MHz / (2 x 60 MHz) = 1.3.
The highest FCCO frequency criteria produces P = 2.67.
The only solution for P that satisfies both of these requirements is P = 2.
Therefore, PLLCFG[6:5] = 1 will be used.

system control block functions


39

APB/VPB divider:
The APB Divider determines the relationship between the
processor clock (CCLK) and the clock used by peripheral
devices (PCLK).
The APB Divider serves two purposes.
The first is to provides peripherals with desired PCLK via
APB bus so that they can operate at the speed chosen for the
ARM processor. In order to achieve this, the APB bus may be
slowed down to one half or one fourth of the processor clock
rate. Because the APB bus must work properly at power up,
the default condition at reset is for the APB bus to run at one
quarter speed.

system control block functions


40

The second purpose of the APB Divider is to allow power


savings when an application does not require any peripherals
to run at the full processor rate.
The connection of the APB Divider relative to the oscillator
and the processor clock. Because the APB Divider is
connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.

ARM7 Based Microcontroller LPC2148:


Pin connect block
41

The pin connect block allows selected pins of the


microcontroller to have more than one function. Configuration
registers control the multiplexers to allow connection between
the pin and the on chip peripherals.
Peripherals should be connected to the appropriate pins prior
to being activated, and prior to any related interrupt(s) being
enabled.
Activity of any enabled peripheral function that is not mapped
to a related pin should be considered undefined.
Selection of a single function on a port pin completely
excludes all other functions otherwise available on the same
pin.

Pin connect block


42

The only partial exception from the above rule of exclusion is


the case of inputs to the A/D converter. Regardless of the
function that is selected for the port pin that also hosts the A/D
input, this A/D input can be read at any time and variations of
the voltage level on this pin will be reflected in the A/D
readings.
However, valid analog reading(s) can be obtained if and only
if the function of an analog input is selected. Only in this case
proper interface circuit is active in between the physical pin
and the A/D module.
In all other cases, a part of digital logic necessary for the
digital function to be performed will be active, and will
disrupt proper behavior of the A/D.

Pin connect block


43

Pin function Select register 0 (PINSEL0 - 0xE002 C000)


The PINSEL0 register controls the functions of the pins as per
the settings listed in Table The direction control bit in the
IO0DIR register is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled
automatically

Pin connect block


44

Pin function Select register 1 (PINSEL1 - 0xE002 C004)


The PINSEL1 register controls the functions of the pins as per
the settings listed in following tables. The direction control bit
in the IO0DIR register is effective only when the GPIO
function is selected for a pin. For other functions direction is
controlled automatically

Pin connect block


45

Pin function Select register 2 (PINSEL2 - 0xE002 C014)

The PINSEL2 register controls the functions of the pins as per the
settings listed in Table. The direction control bit in the IO1DIR
register is effective only when the GPIO function is selected for a
pin. For other functions direction is controlled automatically

Pin connect block


46

Warning: use read-modify-write operation when accessing


PINSEL2 register.
Accidental write of 0 to bit 2 and/or bit 3 results in loss of
debug and/or trace functionality! Changing of either bit 2 or
bit 3 from 1 to 0 may cause an incorrect code execution!
The Debug modes are entered as follows:
During reset, if P1.26 is pulled low (weak bias resistor is
connected from P1.26 to Vss), JTAG pins will be
available.
During reset, if P1.20 is pulled low (weak bias resistor is
connected from P1.20 to Vss), Trace port will be available.

Pin connect block


47

Reset value for bit 2 of PINSEL2 register will be inverse of


the external state of the P1.26/RTCK. Reset value for bit 2
will be set to 1 if P1.26/RTCK is externally pulled low and
reset value for bit 2 will be set to 0 if there is no pull-down.
Reset value for bit 3 of PINSEL2 register will be inverse of
the external state of the P1.20/TRACESYNC. Reset value for
bit 3 will be set to 1 if P1.20/TRACESYNC IS externally
pulled low and reset value for bit 3 will be set to 0 if there is
no pull-down.

ARM7 Based Microcontroller LPC2148:


GPIO
48

Features
Every physical GPIO port is accessible via either the group of
registers providing an enhanced features and accelerated port
access or the legacy group of registers
Accelerated GPIO functions:
GPIO registers are relocated to the ARM local bus so that the
fastest possible I/O timing can be achieved
Mask registers allow treating sets of port bits as a group,
leaving other bits unchanged
All registers are byte and half-word addressable
Entire port value can be written in one instruction

GPIO
49

Bit-level set and clear registers allow a single instruction set


or clear of any number of bits in one port
Direction control of individual bits
All I/O default to inputs after reset
Backward compatibility with other earlier devices is
maintained with legacy registers appearing at the original
addresses on the APB bus

GPIO
50

LPC2141/2/4/6/8 has two 32-bit General Purpose I/O ports.


Total of 30 input/output and a single output only pin out of 32
pins are available on PORT0.
PORT1 has up to 16 pins available for GPIO functions.
PORT0 and PORT1 are controlled via two groups of 4
registers
Legacy registers shown in Table allow backward
compatibility with earlier family devices, using existing code.
The functions and relative timing of older GPIO
implementations is preserved.

GPIO
51

ARM7 Based Microcontroller LPC2148:


Timer
52

The Timer/Counter is designed to count cycles


of the peripheral clock (PCLK) or externallysupplied clock, and
Can optionally generate interrupts or perform
other actions at specified timer values

ARM7 Based Microcontroller LPC2148:


Timer
53

Features:
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Counter or Timer operation
Timer/Counter0 and Timer/Counter1 are functionally
identical except for the peripheral base address.
Four 32-bit capture channels/ timer - Take a snapshot of the timer value
when an input signal transitions.

Optionally generate an interrupt.

Four 32-bit match registers- allow:


Continuous operation with optional interrupt generation on match.
Stop / Reset timer on match with optional interrupt generation.

Timer
Features
54

Four external outputs corresponding to match registers,


with the following capabilities:
Set low on match.
Set high on match.
Toggle on match.
Do nothing on match.

Timer
Pin description
55

CAP0.3..0 & CAP1.3..0 (Input)


Capture Signals- A transition on a this (capture) pin is found, it
loads one of the Capture Registers with the value in the Timer
Counter and optionally generate an interrupt.
When more than one pin is selected for a Capture input on a
single TIMER0/1 channel, the pin with the lowest Port
number is used.
If for example pins 30 (P0.6) and 46 (P0.16) are selected for
CAP0.2, only pin 30 will be used by TIMER0 to perform
CAP0.2 function.

Timer
Pin description
56

List of all CAPTURE signals, together with pins on where they


can be selected:
CAP0.0 (3 pins) : P0.2, P0.22 and P0.30
CAP0.1 (1 pin) : P0.4
CAP0.2 (3 pin) : P0.6, P0.16 and P0.28
CAP0.3 (1 pin) : P0.29
CAP1.0 (1 pin) : P0.10
CAP1.1 (1 pin) : P0.11
CAP1.2 (2 pins) : P0.17 and P0.19
CAP1.3 (2 pins) : P0.18 and P0.21

Timer
Pin description
57

MAT0.3..0 & MAT1.3..0 (Output)


External Match Output 0/1- When a match register
0/1 (MR3:0) equals the timer counter (TC), this
output can either toggle, go low, go high, or do
nothing.
The External Match Register (EMR) controls the
functionality of this output.
It is also possible for example, to have 2 pins selected
at the same time so that they provide MAT1.3
function in parallel.

Timer
Pin description
58

List of all MATCH signals, together with pins on where they


can be selected:
MAT0.0 (2 pins) : P0.3 and P0.22
MAT0.1 (1 pin) : P0.5
MAT0.2 (2 pin) : P0.16 and P0.28
MAT0.3 (1 pin) : P0.29
MAT1.0 (1 pin) : P0.12
MAT1.1 (1 pin) : P0.13
MAT1.2 (2 pins) : P0.17 and P0.19
MAT1.3 (2 pins) : P0.18 and P0.20

Timer
Register description
59

IR- Interrupt Register (Read/Write)


The IR can be written to clear interrupts. The IR can be read to identify
which of eight possible interrupt sources are pending.
TCR- Timer Control Register (Read/Write)
The TCR is used to control the Timer Counter functions. The Timer
Counter can be disabled or reset through the TCR.
TC- Timer Counter (Read/Write)
The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is
controlled through the TCR.

Timer
Register description
60

PR -Prescale Register (Read/Write)


The Prescale Counter (below) is equal to this value, the next clock
increments the TC and clears the PC.
PC- Prescale Counter (Read/Write)
The 32-bit PC is a counter which is incremented to the value stored in
PR. When the value in PR is reached, the TC is incremented and
the PC is cleared. The PC is observable and controllable through
the bus interface.

Timer
Register description
61

MCR- Match Control Register (Read/Write)


The MCR is used to control if an interrupt is generated and if the
TC is reset when a Match occurs.
MR0 MR3 (Match Register 0 -3) (Read/Write)
MR can be enabled through the MCR to reset the TC, stop both
the TC and PC, and/or generate an interrupt every time MR
matches the TC.
CCR- Capture Control Register (Read/Write)
The CCR controls which edges of the capture inputs are used to
load the Capture Registers and whether or not an interrupt is
generated when a capture takes place.

Timer
Register description
62

CR0-3 (Capture Register 0-3) (Read only)


CR is loaded with the value of TC when there is an event on the
CAPn.0/1/2/3(CAP0.0/1/2/3 or CAP1.0/1/2/3 respectively) input.
EMR (External Match Register) (Read/Write)
The EMR controls the external match pins MATn.0-3 (MAT0.0-3
and MAT1.0-3 respectively).
CTCR (Count Control Register) (Read/Write)
The CTCR selects between Timer and Counter mode, and in
Counter mode selects the signal and edge(s) for counting.

Interfacing with LED


63

Program LED Interface


64

#include<lpc21xx.h>
void delay_led(void)
{
unsigned int j;
for(j=0;j<1000000;j++);
return;
}
int main (void)
{
IODIR0 = 0x007F8000;
while (1)
{
IOSET0=0x007F8000;
delay_led();
IOCLR0=0x007F8000;
delay_led();
}
}

/* Define direction of port 0 as (output) I/O pins */


/* Loop forever */
/* turn LEDs ON */
/* Delay */
/* turn LEDs OFF */
/* Delay */

LCD Interfacing
LCD pin description
65

66

Vcc, Vss and VEE :


Vcc= +5V
Vss= Ground
VEE =Controlling LCD contrast

Rs, register select:


Rs = 0; instruction command code register is selected.
Rs = 1; data register is selected.

R/W, read/write:
R/W= 1 Reading
R/W= 0 Writing

67

E, enable:
Latch information presented to its data pins.
When data is supplied to data pins, a high-to-low pulse must be applied to
the En pin in order for the LCD to latch in the data present at the data pins.
(450 nsec)

D0-D7:
Used to send information to the LCD or read the content of the LCDs.

Sending command and data to LCD


68

1.

Time delay (5 to 10 ms)

2.

Busy flag

Busy Flag:
RS=0
R/W=1
When
D7=1; LCD is busy taking care of internal operation
D7=0; LCD is ready to receive new information

69

70

LCD Interface to LPC 2148


71

Keypad
72

General Operation of a Keypad


73

The aim of this mechanism is to generate and transmit a code


each time a key is pressed
The mechanism should send one and only proper code, when
the key is pressed
It is used to input data or program into the microcomputer
It consider of push button type switches
When a key is pressed, the microcontroller identifies key
depression and then perform appropriate operation
The input keyboard is composed of a set of labeled push
button switches. Each switch makes electrical contact when
pressed

Bouncing of Key Switch


74

In case of a push button key , the metal contact


bounces few times, hence the voltage across the
switch fluctuates and generates spikes in the
signal . Therefore it is necessary to debauched the
mechanical switches. This is called key
debounceing
The key debouncing is done through hardware
and software

Hardware Key debouncing


75

Hardware Key debouncing


76

It is implemented by using flip flop or latch


When the switch is connected to A , the output of
the latch goes high. When the key makes contact
with B , the output changes from logic 1 to logic 0
The wiper bounces many times on contact B, but
the output does not fluctuate between logic 1 and
logic 0
When the wiper is not connected either to A or B ,
the output of the latch remains constant

Software Key Debouncing


77

START
Read
Keyboard
Is
Key
Presse
d?
Delay 20
ms
Is
Key Still
Pressed?
Accept Key
Ret

Software Key Debouncing


78

In the software technique the microcontroller waits


for 20 ms before it accepts the key as an input
If after 20 ms the key is pressed the key is accepted
by microcontroller

79

Programming for keypad interfacing


In Programming for keypad interfacing we must have two processes
1. Key press detection
2. Key identification
There are two ways by which the PIC18 can perform key press
detection
a) The interrupt method
b) The scanning method

80

81

82

83

Flow chart for Scanning Method


for Key Press Detection

84

LCD & KEYPAD INTERFACE CODE


#include<lpc21xx.h>
/* Keypad Connection:
P0.4,P0.5,P0.6,P0.7 ---Col---Read Lines
P0.8,P0.9,P0.10,P0.11 ---Row---Scan Lines
LCD:
RS---P1.20
EN---P1.21
Data--P0.12 to P0.19 */
void lcdcmd(unsigned int);
void lcddata(unsigned int);
void delay_lcd(void);

85

void lcdcmd(unsigned int cmddata)


{
IOCLR0=0x000ff000;
IOCLR1=(1<<20);
cmddata=cmddata<<12;
IOSET0=cmddata;
IOSET1=(1<<21);
delay_lcd();
IOCLR1=(1<<21);
delay_lcd();
return;
}

86

87

void lcddata(unsigned int outdata)


{
IOCLR1=0x000ff000;
IOSET1=(1<<20);
outdata=outdata<<12;
IOSET0=outdata;
IOSET1=(1<<21);
delay_lcd();
IOCLR1=(1<<21);
delay_lcd();
return;
}
void delay_lcd(void)
{
int j;
for(j=0;j<10000;j++);
return;
}

int main(void)
{
IODIR1=0x00300000;
IODIR0=0x000FF0F0;
lcdcmd(0x38);
delay_lcd();
lcdcmd(0x0e);
delay_lcd();
lcdcmd(0x01);
delay_lcd();
lcdcmd(0x06);
delay_lcd();
88

while(1)
{
lcdcmd(0x83);
delay_lcd();
// lcdcmd(0xC0);
IO0PIN=0x00000F70;
// Second Scan Line
if(( IO0PIN & 0x00000F70 )!= 0x00000F70)
{
switch(IO0PIN & 0x00000F70)
{
case 0x00000E70 : lcddata('A');break;
case 0x00000D70 : lcddata('B');break;
case 0x00000B70 : lcddata('C');break;
case 0x00000770 : lcddata('D');break;
}
}
89

IO0PIN=0x00000FB0;
// Second Scan Line
if(( IO0PIN & 0x00000FB0 )!= 0x00000FB0)
{
switch(IO0PIN & 0x00000FB0)
{
case 0x00000EB0 : lcddata('3');break;
case 0x00000DB0 : lcddata('6');break;
case 0x00000BB0 : lcddata('9');break;
case 0x000007B0 : lcddata('F');break;
}
}

90

IO0PIN=0x00000FD0;
// Second Scan Line
if(( IO0PIN & 0x00000FD0 )!=
0x00000FD0)
{
switch(IO0PIN & 0x00000FD0)
{
case 0x00000ED0 : lcddata('2');break;
case 0x00000DD0 : lcddata('5');break;
case 0x00000BD0 : lcddata('8');break;
case 0x000007D0 : lcddata('0');break;
}
}

91

IO0PIN=0x00000FE0;
// Second Scan Line
if(( IO0PIN & 0x00000FE0 )!= 0x00000FE0)
{
switch(IO0PIN & 0x00000FE0)
{
case 0x00000EE0 : lcddata('1');break;
case 0x00000DE0 : lcddata('4');break;
case 0x00000BE0 : lcddata('7');break;
case 0x000007E0 : lcddata('E');break;
}
}
delay_lcd();
}
}

92

Graphic LCD
93

Introduction
JHD12864E Graphic LCD Module
Based on KS107/KS108 LCD Controller
128x 64 dots/pixel
8-bit Parallel Interface
No. Data Lines : 08
No. Control Lines: 06
Display is Split logically in half
Each Half is controlled by Separate Controller

94

GLCD Signals
LCD Data Lines (D0 D7)
8-bit bidirectional data bus
Used to send information to the LCD
Read the contents of internal registers
LCD Control Lines
RS: Select Data register or a Command/Status register.
R/W#: Read/Write select control line.
E: Latches information presented to its
CS1 & CS2: Chip Select Signals
Reset : LCD Reset signal

95

GLCD Pin Configuration


96

Instruction Set
97

98

GLCD Registers
GLCD Input Register is used while giving
instructions and writing data to LCD.
It holds the data/instruction temporarily before
writing to DDRAM (Data Display RAM).
GLCD Output Register is used to read data from
DDRAM and to check status data (busy check).

99

When the LCD is in active mode (CS1 and CS2


high), the registers can be selected by sending bits
on RS and RW pins as shown in the following
table.

GLCD Basic Operations


100

GLCD Initialization
Page Selection
Column Selection
Data Display

101

GLCD Initialization

3E = LCD OFF (D=0); 3F = LCD ON (D=1)


CS1=1, CS2=1 (to activate display of both halves)
RS=0, R/W=0
EN=1
Delay More than15ms
EN=0 (to latch data into the input register): H to L transition

102

Page Selection

CS1=1, CS2=1 (to activate display of both halves)


RS=0, R/W=0 (to select the instruction mode)
EN=1
Delay
EN=0 (to latch data into the input register)

103

Column Selection

RS=0, R/W=0 (to select the instruction mode)


EN=1
Delay
EN=0 (to latch data into the input register)

104

Column Selection
The corresponding controller (CS1 or CS2) is
selected depending on the Column number

105

Data Display

With every write cycle, data is written in one column and the
column then gets auto-incremented.
Here MSB corresponds to 8th row in column and LSB to 1st row
of column.
RS=1 and R/W=0 (to select write mode of LCD)
EN=1, Delay, EN=0.

GLCD Interface
106