B.E.

(EC) Semester VI

CMOS VLSI DESIGN

Advanced CMOS Circuits

BiCMOS Technology
BiCMOS
CMOS
Low power dissipation

BIPOLAR
High speed

High packing density

High
Combines
Bipolar drive
and CMOS transistors in a single integrated circuit
output
Introduced in early 1980s
By retaining benefits of bipolar and CMOS, BiCMOS is able to
achieve VLSI circuits with speed-power-density performance
previously unattainable with either technology individually.

Characteristics of CMOS Technology

Lower static power dissipation
Higher noise margins
Higher packing density lower manufacturing cost per device
High yield with large integrated complex functions
Advantages of CMOS over bipolar

High input impedance (low drive current)

Scalable threshold voltage
High delay sensitivity to load (fan-out limitations)
Low output drive current (issue when driving large capacitive loads)
Low transconductance, where transconductance, gm Vin
Bi-directional capability (drain & source are interchangeable)
A near ideal switching device

Characteristics of Bipolar Technology

Advantages of Bipolar over CMOS

Higher switching speed

Higher current drive per unit area, higher gain
Generally better noise performance and better high frequency characteristics
Better analogue capability
Improved I/O speed (particularly significant with the growing importance of
package limitations in high speed systems).
high power dissipation
lower input impedance (high drive current)
low voltage swing logic
low packing density
low delay sensitivity to load
high gm (gm Vin)
high unity gain band width (ft) at low currents
essentially unidirectional

WHY BiCMOS ??

Speed

For greater integration of mixed-signal analog

systems
To cover full delay-power space
BiPOLAR

BiCMOS
Power

CMOS

Combine advantages in BiCMOS Technology

It follows that BiCMOS technology goes some way towards combining the virtues
of both CMOS and Bipolar technologies
Design uses CMOS gates along with bipolar totem-pole stage where driving of high
capacitance loads is required
Resulting benefits of BiCMOS technology over solely CMOS or solely bipolar :
Improved speed over purely-CMOS technology
Lower power dissipation than purely-bipolar technology (simplifying
packaging and board requirements)
Flexible I/Os (i.e., TTL, CMOS or ECL)
BiCMOS technology is well suited for I/O intensive applications.
ECL, TTL and CMOS input and output levels can easily be generated with no
speed or tracking consequences
high performance analogue
Latchup immunity

BASIC BiCMOS INVERTER

CIRCUIT DIAGRAM
VDD

OP

GND

Adapted from J. M Rabaey, Digital Integrated Circuits: A Design

Prespective,New Jersey: Prentice-Hall, Inc., 1996.

PULL UP/PULL DOWN EVENT

PULL UP PATH
Vin = 0
M2 ON , Q2 ON , CL Charging
Through Q2 .
Input to Q2 ensure M3 ON
which in turn ensure Q1 OFF
PULL DOWN PATH
Vin = 1
M2 OFF , M4 ON ensure Q2 and
M3 OFF
M1 ON which in turn connect
Vout to the Q1 Base . Higher Vout
turn
on
Q1
and
allow
discharging till Vout = VBE
Adapted from Sung-Mo Kang,Yusuf Leblebici,CMOS Digital
Integrated Circuits: Analysis and Design,Tata McGraw-Hill,Third
edition,2003,p.547/550.

VTC

DYNAMIC CHARACTERISTICS

CMOS

BiCMOS

BiCMOS CROSS-SECTION

Adapted from J. P. Uremuya, Circuit Design for CMOS VLSI,

Massachusetts: Kluwer Academic Publishers, 1992.

Velocity Saturation / Lower doping Density

Particle Diffusion

Improved speed over CMOS

Improved current drive over CMOS
Improved packing density over
bipolar
Lower power consumption than
bipolar
High input impedance
Low output impedance
Increased manufacturing
process complexity
Speed degradation due to
scaling
Full custom ICs
SRAM,DRAM
Microprocessor, controller
Semi custom ICs
Register, Flip-flop
Standard cells
Adders, mixers, ADC,DAC
Gate arrays

General Form of a BiCMOS

Circuit
DRAW BiCMOS NAND2 CIRCUIT

PUN

PDN

Advanced CMOS Circuits

What makes a circuit fast?
I = C dV/dt

-> tpd (C/I) V B

low capacitance
high current
small swing

Y
1

Logical effort is proportional to C/I

pMOS are the enemy!
High capacitance for a given current
Can we take the pMOS capacitance off the
input?
Various circuit families try to do this

Psuedo-nMOS
In CMOS , PUN is replaced with a single pMOS ,
which is always ON (i.e. input is grounded )
PDN network based on input combination tries
to pull down the output.
Resistance of PDN must be less than the
resistance of pMOS, to ensure low output
voltage near to 0.
Referred as ratioed logic. n/p > > > > 1.
High power dissipation , High packing density.
Less number of transistors so cost is low.
Problems : 1) VOL is not 0 .
2) High static power consumption.
Advantages : ????

LIST OUT

Tri-State Circuits/Clocked CMOS Logic

(C2MOS)

Clocking transistors allow

valid logic output only when
clk is high
Clocking transistors may be
at output end of logic trees
(maximum performance) or
at power supply end of logic
trees (maximum protection
from hot electrons)
Useful for isolating circuits from
common bus lines.
Unless inputs get stabilized , evaluation
of logic is abandoned.
Draw Si layout for Tri state buffer.

Dynamic Logic
Dynamic gates uses a clocked
pMOS pullup
Two modes: precharge and

2
2/3
1
evaluate
A

1
Static

Precharge

4/3

Pseudo-nMOS

Evaluate

Dynamic

Precharge

The Foot
What if pulldown network is ON
during precharge?
Use series evaluation transistor to
prevent fight.

precharge transistor
Y

inputs

Y
f

inputs

Y
f

A
foot

footed

unfooted

Monotonicity
Dynamic gates require
monotonically rising inputs during
evaluation

0 -> 0
0 -> 1
1 -> 1
But not 1 -> 0

violates monotonicity
during evaluation

Precharge

Evaluate

Precharge

Y
Output should rise but does not

Monotonicity Woes
But dynamic gates produce
monotonically falling outputs during
evaluation
Illegal for one dynamic gate to drive
another! A = 1

Precharge

Evaluate

Precharge

X
X monotonically falls during evaluation
Y
Y should rise but cannot

Domino Gates
Follow dynamic stage with inverting
static gate
Dynamic / static pair is called domino gate
Produces monotonic outputs

domino AND

Precharge

Evaluate

Precharge

A
B

Y
Z

dynamic static
NAND inverter

A
B

H
C

A
B

X
C