20-NM TECHNOLOGY

in MICROWIND
Etienne.sicard@insa-toulouse.fr

MICROWIND APPLICATION NOTES

Technolog
y node

90nm
65nm
45nm
32/28nm
20nm

14nm

Year of
Key Innovations
introduct
ion
2003
SOI substrate
2004
Strain silicon
2008
2nd generation
strain, 10 metal
layers
2010
High-K metal gate
2013
Replacement metal
gate, Double
patterning, 12 metal
layers
2015
FinFET

www.microwind.org > Application Notes

20-NM APPLICATION NOTE

The Joint Development

Alliance has released in
2012 a 20-nm technology

Microwinds 20-nm rule file

has been tuned to the JDA
20-nm technology based
on available publications

This application note

Technology

130nm

90nm

100M

250M

45nm

Complexity
500M

28nm

17nm

5nm

2G

7G

150 G

Packaging

Mobile
generation

Embedded
blocks

3G

3G+

200
4

2007

Core+
Core+
DSP
DSP

Core
Core
DSPs
DSPs

11Mb
Mb
Mem
Mem

10
10Mb
Mb
Mem
Mem

2010
Dual
Dualcore
core
Dual
DSP
Dual DSP
RF
RF
Graphic
Graphic
Process.
Process.
100
100Mb
MbMem
Mem
Sensors
Sensors

5G

4G+

4G
2013

2016

Quad
QuadCore
Core
Quad
DSP
Quad DSP
3D
3DImage
ImageProc
Proc
Crypto
Cryptoprocessor
processor
Reconf
ReconfFPGA,
FPGA,
Multi
MultiRF
RF
11Gb
Memories
Gb Memories
Multi-sensors
Multi-sensors

2020
??

TOWARDS 10GT

100000000000

10 GT in 2015
10000000000

This
application
note

1 GT in 2010

1000000000

Multi-core

Transistor count

Quadcor
e

100000000

Dual
core

10000000

130nm
0.18u
0.25u
0.35u
0.5u

16
bit

10000

8-bit
1000
1960

1970

1980

40nm
90nm

32
bit

100000

30nm
65nm

64bit
1000000

20nm

1990

2000

2010

2020

MOS CURRENT DRIVE

FinFET for
increasing drive
current and
reducing leakage

High K Metal Gate

to increase field
effect

MOS
Current
drive
(mA/m)

Strain to increase
mobility

This
applicatio
n note

Hig
per h
f
ma or
nce

2.0

l
Genera
e
Purpos

1.5
1.0

Ioff:
100nA/m

Low
power

10nA
1 nA

0.5
0.0
130 nm

90 nm

65 nm

Intrinsic performances

45 nm

32 nm

Gate material
Strain

20 nm

14 nm

10
nm

Technology node

SCALE DOWN BENEFITS

Smaller

Faster

Less power

90nm

consumption

45nm

Cheaper (if you

fabricate millions)

20nm
Power
-50%
90nm

45nm

-80%
20nm

SCALE DOWN BENEFITS

Maximum die size

One
cor
e
One Core

AMD dual core 65nm

8 cores instead of 1 using the same space

3 times faster

10 times less power consumption

Intel Octa core 22nm

SUPPLY VOLTAGE SCALE DOWN

This
application
note

Supply (V)
5.0

3.3

0.9 V
inside,
1.5V
outside

I/O supply

2.5

Core supply

1.8
1.2
1.0

0.35

0.18

130n

90n

65n

45n

32n

Technology node

20n

14n

10n

7n

REFERENCE PUBLICATIONS

High Performance
Bulk Planar 20nm
CMOS Technology
for Low Power
Mobile Applications,
Huiling Shang, 2012
Symposium on VLSI
Technology

Used as a reference
for Microwinds 20nm
implementation

PERFORMANCE TARGETS

Only a subset of 20-nm variants has been implemented in Microwind

Parameter

Value

VDD core (V)

Effective gate length
(nm)
MOS variants
Ion N (mA/m) at VDD

0.9
20
5
0.7-1.2

Ion P (mA/m) at VDD 0.7-1.4

Ioff N (nA/m)
Ioff P (nA/m)
Gate dielectric
Gate stack
Equivalent oxide

0.06-200
0.06-200
HfO2
Al/TiN
1

In
Microwind
0.9
20
2
0.9 (LL) 1.1
(HS)
0.8 (LL) 1.0
(HS)
1 (LL) 10 (HS)
1 (LL) 10 (HS)
HfO2
Al/TiN
1

NMOS 20nm

Iof (nA/m)

10

100

Microwind
s High
speed

10

Microwinds
Low
Leakage

sLVT

1.0

LVT
RVT

0.1

Microwind
s High
speed

uLVT

Iof (nA/m)

100

PMOS 20nm

Microwinds
Low
Leakage

uLVT

sLVT
LVT

1.0

RVT

0.1

HLVT

HLVT
0.01

0.01
0.5

1.0
Ion (mA/m)

1.5

0.5

1.0
Ion (mA/m)

1.5

MOS DEVICE

6 min.
metal pitch
(here 8 )

Paramet
er
Lambda
Minimum
gate
length
Minimum
gate
width
Metal
pitch

20-nm
technolo
gy

20 nm

In
Microwin
d
11 nm
2 (22
nm)

60 nm

6 (66
nm)

64

6 (66
nm)

6
minimum
width
(here 10
)

2
minimum
gate
length

3 min for
metal 1
(here 4 )

MOS 2D CROSS-SECTION

Aluminum fill

Hf02based
high-k
oxide

Al

N+ diffusion

Aluminum fill

Work-function
metal based
on TiN

N+ diffusion
P-doped substrate

20-nm Nchannel MOS

without strain

Hf02based
high-k
oxide

Al

P+ diffusion
(eSiGe)

Work-function
metal based
on TiN

P+ diffusion
(eSiGe)
N-doped well

20-nm Pchannel MOS

with strain

20-NM PROCESS VIEW

N-channel
MOS

P-channel
MOS

MOS VARIANTS

Ion=1.1m
A

Ion=0.9mA

Microwinds Low
Leakage NMOS
(RVT)

Microwinds High
speed NMOS
(SLVT)

Low-leakage
nMOS

The option
layer
enables to
changes the
MOS option
High-Speed
nMOS

ION/IOFF TRADE-OFF

Id/Vg for Vb=0, Vds=0.9

V

Id/Vg for Vb=0, Vds=0.9

V

Ion=1.1m
A

Ion=0.9mA

Vt=0.35
V
Ioff=1 nA

Microwinds Low
Leakage NMOS
(RVT)

Vt=0.30
V
Ioff=10
nA

Microwinds High
speed NMOS
(SLVT)

ION BENEFITS

Ion=1.0m
A
Ion=0.8mA

Microwinds Low
Leakage NMOS
(RVT)

Microwinds High
speed NMOS
(SLVT)

PMOS TRADE-OFF

Id/Vg for Vb=0, Vds=0.9

V

Id/Vg for Vb=0, Vds=0.9

V

Ion=1.0m
A

Ion=0.8mA

Vt=0.35
V
Ioff=1 nA

Microwinds Low
Leakage PMOS
(RVT)

Vt=0.30
V
Ioff=10
nA

Microwinds High
speed PMOS (SLVT)

DUMMY POLY

Dummy gates for increased

manufacturability

DUMMY POLY

Severe
distortion

Reduced
distortion

METAL LAYERS

Only 8 metal layers available in Microwind

Re-assignement of original 11 layers, as close as possible to the original pitch

Parameter

Pitch
(nm)
64

Thickness Pitch in
(nm)
Microwind
50
Not supported

64

68

M4-M7

80

80

M8-M9

358

150

M10-M11

1000

200

Middle-of-theLine (MOL)
M1-M3

Purpose

Intra-cell
routing
M1-M2: 6 (66 Short routing
nm)
M3-M4: 8 (88 Medium
nm)
routing
M5-M6: 32
Block supply
and long
routing
M7-M8: 92
System
supply and IO
routing

METAL LAYERS

DOUBLE PATTERNING

For pitch lower

than 80nm (M2M8): simple
patterning

For pitch lower

than 80nm (M1M2): double
patterning

DOUBLE PATTERNING

Initial M1
layer
6 minimum
pitch

Bridge

After
fabrication in
single
patterning

Open

DOUBLE PATTERNING

66 nm pitch M1
patterns need
double patterning

First
patterning

Second
patterning

RING OSCILLATOR STUDY

Publication

A. Scholze Exploring MOL Design Options for

a 20nm CMOS Technology using TCAD,
SISPAD 2011

Design in
Microwind

RING OSCILLATOR STUDY

RING OSCILLATOR STUDY

With a fanout of 3, around 5ps/stage

Only small gain as compared to

32/28-nm node

PROCESS, TEMPERATURE, SUPPLY

VARIATIONS

Worst case
conditions
Best case
conditions

PROCESS, TEMPERATURE, SUPPLY

VARIATIONS

5-stage Ring Oscillator

Frequency (FO3) in GHz

70
60
HS-sLVT
50

300%
differenc
e

40
LL-RVT
30
20
10

Worst case
conditions:
slow, high
T, low
supply

Min

Typ
PVT

Max

Best case
conditions
Fast, low
T, high
supply

6-TRANSISTOR MEMORY

Shared
contacts

0.08 m2

Shared
supply

CONCLUSION

Major foundries have cooperated to release a common 20-nm technology in 2012

Microwinds 20-nm rule file has been tuned to this joint technology

VDD passes below the 1V barrier

2 MOS device options implemented: high speed & low leakage

Aggressive 64nm lower metal pitch require double patterning

Dummy poly added for improved manufacturability

Inverter delay with Fanout 3 around 5ps

Up to 300% performance variations in extreme PVT conditions

Future nodes will require FinFET device

Thank you for your attention

Etienne.sicard@insa-toulouse.fr