Computer Operation

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Sequential Machine
A digital computer is a sequential machine.
The CPU (microprocessor) executes instructions in a
sequence as specified by the program.
In general terms the instructions are executed in the
sequence they are written.
However a certain class of instruction can vary the
instruction execution sequence.
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Function of Memory System

The function of the memory system of a
digital computer is :
Provide a storage facility for the program ( the
instructions ) the microprocessor is required to
execute.
Provide a storage facility for the data that
is to be manipulated by those instructions.
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The Instruction Cycle

There are two stages to the complete execution of an
instruction :
Stage 1 : CPU fetches the instruction from memory
Stage 2 : CPU executes the instruction

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Instruction Fetch
Processor places address
of where the instruction is
stored onto address bus
Processor asserts the read
control line
The memory device places
the data at the addressed
location onto the data bus
The processor reads the
instruction byte.

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Instruction Format
Instructions are stored in program
memory in binary coded form.
Since an instruction must represent a
complete and unambiguous statement of
the operation required of the processor
then 8-bits (the number of bits of a single
memory location) is often insufficient to
specify the complete instruction.
Depending on the particular instruction,
8085A instructions occupy one, two or
three successive memory locations.

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The Opcode
The first byte of an instruction is called the
Opcode
It describes :
The operation to be carried out e.g move data,
arithmetic operation, logical operation etc
Where the source data is located in the computer
The destination for the result of the operation
How many bytes constitute the complete instruction
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Example of Opcode
Consider the instruction: STA addr
Opcode in assembly language form STA
Opcode in machine language form (i.e. the bits that are actually stored in memory) 00110010 (32H)
The opcode specifies :

Data is to be moved
The source of the data is the CPU register A
The destination for the data is external memory
The complete instruction is three bytes long
Bytes 2 & 3 of the instruction specify the address of the memory location
where the data is to be written.

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Where the Opcode is Stored in the

CPU
Once read from memory, the opcode of the instruction is stored in the instruction
register (an 8-bit register) of the CPU .

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Instruction Decoder and Control

Logic
The contents of the instruction register is read by the instruction
decoder.
The instruction decoder configures the control logic so that the
particular sequence of CPU operations are carried out to
complete execution of the instruction.
This will include fetching the remaining bytes of an instruction, if
the instruction is a multibyte instruction.
The second ( and third ) bytes of a multibyte instruction are
accessed by the CPU in exactly the same way as the opcode is
fetched from memory. The second ( and third ) bytes of an
instruction are stored in temporary registers in the CPU.

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The Program Counter

The program counter is a 16-bit CPU register.
The program counter always contains the address of the memory
location from where the CPU is to fetch the next instruction byte.
The program counter is automatically incremented every time the
CPU fetches an instruction byte. Instructions are thus executed in
the sequence they are loaded into program memory.
The contents of the program counter can be overwritten by
execution of certain instructions e.g. jmp, call, ret etc.
The program counter is initialised to 0000H after processor reset
or on power-up.

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Example of Instruction
Execution
The following are the sequence of operations the processor is
required to perform to execute the instruction
STA addr

Place program counter onto address bus ; opcode address

Assert RD control signal
Read opcode and load into instruction register
; PC incremented
Decode the opcode
Place program counter onto address bus ; address of byte 2
Assert RD control signal
Read byte 2 and save in temp register W ; PC incremented
Place program counter onto address bus ; address of byte 3
Assert RD control signal
Read byte 3 and save in temp register X ; PC incremented

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Example of Instruction
Execution

The whole of the instruction has been fetched at this stage. The 8bit temporary registers W & X contain the 16-bit address of the
memory location at which the contents of CPU register A is to be
stored.
The execution phase of the instruction can now take place.

Place the contents of W & X onto the address bus ; specify memory address
Place the contents of register A onto data bus
; data to be written
Assert WR control signal
; write data to memory

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8085 Internal Architecture

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 The register file :

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The Register File

6X 8-bit registers with addresses B, C, D, E, H & L
Can be concatenated to form 3X 16-bit registers with addresses BC,
DE & HL.
Note : 16-bit register HL used as a memory pointer with many 8085A
instructions.
(e.g MOV A, M which copies the contents of the memory location
whose address is specified by the contents of the HL register
pair to the CPU register A)
(Note the assembly language instruction format
MOV

<destination> <source>)

16-bit register SP. It contains the address of the memory location of

the top of the stack area of memory. It is automatically controlled by
the processor but can be initialised by software.

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How the Stack Works

The stack is a reserved area of memory. It operates as a last-in
first-out bank of registers.
The memory locations, which constitute the stack, are used to
store binary information temporarily during program execution.
The stack can be located anywhere in read/write memory, but is
usually defined such that it neither interferes with the program
memory space or the data memory space.
The start address of the stack is specified at the initialisation
stage of the program by loading the 16-bit CPU register, called
the stack pointer, with the desired address of the start of the
stack.
e.g

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LXI

SP, data 16

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How the Stack Works

Data from CPU register pairs are stored in the stack area of
memory when the processor executes a push rp instruction.
The contents of the program counter is automatically stored in
the stack area of memory whenever the processor executes a
call or restart (rst n) instruction.
Data stored in the stack area of memory are returned to
processor register pairs when the processor executes a pop rp
instruction.
Data is automatically transferred from the stack area of memory
to the program counter whenever the processor executes a
return (ret) instruction.

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Writing to the Stack

To execute the instruction push HL

assuming initial sp contents is 2099
H.

The stack pointer is decremented

by 1 (sp=2098) and the contents of
H are written to this location.

The stack pointer is decremented

by 1 (sp=2097) and the contents of
L are written to this location.

Note : When data is written to the

stack the stack pointer is first
decremented and then the data is
written

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Reading from the Stack

To execute the instruction pop BC

assuming initial sp contents is 2097
H.

The contents of the memory location

at the address specified by the
contents of sp is moved to register C
and sp is incremented.

The contents of the memory location

at the address specified by the
contents of sp is moved to register B
and sp is incremented.

Note : When data is read from the

stack the data is read first and then
the stack pointer incremented.

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Other 8085A CPU Features

The ALU unit

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The ALU Subsystem

More detailed schematic

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The ALU Subsystem

The ALU itself is a group of combinatorial logic circuits that can
perform 8-bit arithmetic and logical operations. Included are :add, sub, and, or, xor
The accumulator ( reg A ) is an 8-bit general purpose register
that holds one of the source operands of an ALU operation. The
result of the operation is also returned to the accumulator.
The temporary accumulator is an 8-bit register that holds the
second operand used in a ALU operation. It is inaccessible to
the user.
The decimal adjust unit allows the ALU to perform BCD
arithmetic. (rarely used as it is usual to use binary, as opposed
to BCD, arithmetic)

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The Flag Register

The flag register is a collection of eight, single bit registers. It

reflects outcomes of arithmetic or logical operations.

The Sign Flag (S) reflects the contents of bit-7 of the accumulator

The Zero Flag (Z) is set to 1 if the accumulator contains all zeros

The Auxiliary Carry (AC) is a 1 if the arithmetic operation caused a

carry out from the bit-3 to the bit-4 position. (The auxiliary carry flag is
used in BCD arithmetic)

The Parity Flag (P) is a 1 if the accumulator has an even number of 1s

The Carry Flag (CY) is set if the arithmetic operation caused a carry
overflow (from addition) or a borrow (from subtraction).

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Example of an Arithmetic Operation

ADD B

; A contains 88 (H)

B contains 99 (H)

register A
10001000
136
decimal register B
10
011001
153
decimal _____________
_____
register A
100100001
289
decimal

S = 0 Bit D7 = 0 after addition

Z = 0 The accumulator contains other than zero after addition
AC = 1
There is a carry out of bit D3 to bit D4 during addition
P = 1 The accumulator contains an even number of 1s
after
addition
CY = 1
There is an overflow as a result of the addition

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More on the Control Logic

The control logic subsystem of a microprocessor is a configurable
sequential state machine.
It is configured by the instruction decoding circuitry to enable
execution of a particular instruction.
It has associated with it a number of inputs and outputs, both from
other subsystems of the CPU and from external devices.
It operates with respect to a stable clock reference signal provided
by a crystal source. Typical clock frequencies for an 8085A
microprocessor are in the order of 5-MHz.
The internal clock for the control logic is half the frequency of the
external crystal source (i.e internally the crystal source clock is
divided by 2)

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Control Logic - External Inputs and

Outputs

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Function of Control Logic Inputs and

Outputs
RD (o) A logic 0 specifies the processor will read
the data on the data bus.

WR (o) A logic 0specifies that the processor has

placed data (write) onto the data bus for
an external device to read.

S0 S1 IO / M (o) A 3-bit status code that specifies the operation the

processor is performing. (e.g 110 specifies the
processor is fetching an opcode from program
memory).

reset out (o) A logic 1 on the reset in input to the processor

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causes the program counter to be reset to 0000H.

To indicate the processor has been reset a logic
`1, synchronised to the processor clock, is placed
on this output.

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Function of Control Logic Inputs and

Outputs

CLK out (o) Is a buffered version of the internal master clock of the
8085A. It is half the crystal frequency.

HOLD (i) HLDA (o) An external device can request use of the system
busses by driving the HOLD input to logic 1. The
8085A acknowledges the request by asserting the
HLDA output to logic 1. It only does after it has
relinquished control of the bus structure.

ALE (o) When this signal is logic 1 the processor specifies that
it has valid address information on the CPU pins AD07

RDY (i) When this signal is logic 0 the processor suspends

execution of an instruction. It permits slow peripheral

devices more time to access or load data.

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8085A Bus Interfaces

The 8085A microprocessor uses only 16 connections
to interface the 8-bit data bus and 16-bit address bus.
Address bus lines A 07 are time multiplexed with
data bus lines D07

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Address Latches
Peripheral devices ( memory and IO ) require stable address
data throughout a read or write operation.
The processor only provides A0 - A7 during the period ALE is in
the logic 1 state after which the multiplexed lines AD0 - AD7
assume the role of the data bus. ( D0 - D7 )
To provide external devices with stable address data throughout
a read or write operation it is necessary to latch the low byte of
the address using the ALE control signal.
By this mechanism it is possible for the 8085A computer system
to have a 16-bit address bus and an 8-bit data bus whilst only
using 16 processor connections ( AD0 - AD7 and A8 - A15 )

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De-multiplexing AD0 - AD7

Note : See through latches ( eg 74LS573 ) are the preferred

type of latch.
When clk (ALE) is logic 1 the latch outputs follow the inputs and on the
negative edge of clk the data is latched.

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