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FEATURES
16byte receive and transmit FIFOS
Register locations conform to 550 industry
standard
Receiver FIFO trigger points at 1,4,8 and 14
bytes
Built in fractional baud rate generator
covering wide range of baud rates without a
need for external crystals of particular values
Transmission FIFO control enables
implementation of software (xon / xoff)flow
control on both uarts
UART 0
FEATURES :
16 byte Receive and Transmit FIFOs
Register locations conform to 550 industry
standard.
Receiver FIFO trigger points at 1, 4, 8, and 14
bytes.
Built-in fractional baud rate generator with
auto bauding capabilities.
Mechanism that enables software and
hardware flow control implementation
UART0 contains registers . The Divisor Latch
Access Bit (DLAB) is contained in U0LCR and
enables access to the Divisor Latches
UART 1
UART1 is identical to UART0, with the
addition of a modem interface.
16 byte Receive and Transmit FIFOs.
Register locations conform to 550 industry
standard.
Receiver FIFO trigger points at 1, 4, 8, and
14 bytes.
Built-in fractional baud rate generator with
auto bauding capabilities.
Mechanism that enables software and
hardware flow control implementation.
Standard modem interface signals included
with flow control (auto-CTS/RTS) fully