Operating System Concepts

Chapter 2
 I/O Mechanisms
Memory controller synchronizes access to
shared memory by CPU and device
controllers.
Device controller is in charge of a specific
type of device, informs on completion by
causing an interrupt
 Interrupts
A signal by a program (trap) or device
Caused by hardware failure, invalid system
access, completion of I/O, system request,
software errors.
Stops whatever is running and transfers control
to a fixed location which contains interrupt
service routine
Detected by
Polling- query devices to detect requests
Vectored interrupt system- uses pointers
 Input/ Output (I/O)
Synchronous
Control returns to user program after I/O has
completed
Asynchronous
Simultaneous I/O & user processing
Return before I/O completion
OS keeps track of all waiting requests
Increased CPU usage
Although I/O speed is slow, work output increases
 Direct Memory Access (DMA)
Used for high speed I/O devices
Delegates information transfer to device
controller without the intervention by the CPU.
CPU free to perform other tasks.
The device controller transfers an entire block of
data to or from its own buffer storage to main
memory. Only one interrupt is generated per
block rather than one interrupt per byte (word)
generated for low speed devices.
CPU interrupted by device after I/O completion
 Data Storage
Run programs in main memory (too small to all
needed programs permanently & temporary
(volatile)) & store in Secondary memory
(magnetic disks, optical disks, magnetic tapes,
e.t.c)
Main memory & registers are the only storage
areas which the CPU can access directly.
Running programs, data in use must be in direct
access devices.
 Hardware Protection
Two modes of operation (dual mode)
Mode bit used to select the mode (0 monitor, 1
user)
User programs restricted to certain areas where
they can not alter system resources
Monitor mode (supervisor/system/privileged)
Operations on behalf of system
Access to system files and memory
User mode
On behalf of user programs
I/O requests results in switch to monitor mode
 I/O protection
I/O privileged instructions to prevent users
from issuing wrong instructions.
All interrupts dealt with in monitor mode
Protection of interrupt vectors from
modification by a user program
Memory is protected using base & limit
registers
To protect the CPU from infinite loops use
a timer